Datasheet

MAX6884/MAX6885
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
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WRITE BYTE FORMAT
SSADDRESS ADDRESS
7 BITS 7 BITS
SEND BYTE FORMAT RECEIVE BYTE FORMAT
WR WRACK ACKDATA DATA
8 BITS 8 BITS
ACK P ACK P
DATA BYTE: PRESETS THE
INTERNAL ADDRESS POINTER
DATA BYTE: READS DATA FROM
THE REGISTER COMMANDED BY
THE LAST READ BYTE OR WRITE
BYTE TRANSMISSION. ALSO
DEPENDENT ON A SEND BYTE.
BLOCK WRITE FORMAT
S ADDRESS
WR ACK COMMAND ACK
BYTE
COUNT = N
BYTE
COUNT = 16
ACK
DATA BYTE
1
DATA BYTE
1
ACK
DATA BYTE
•••
DATA BYTE
•••
ACK
DATA BYTE
N
DATA BYTE
N
ACK P
COMMAND BYTE:
PREPARES DEVICE
FOR BLOCK OPERATION
DATA BYTE: DATA GOES INTO THE REGISTER SET BY THE
COMMAND BYTE
DATA BYTE: DATA GOES INTO THE REGISTER SET BY THE
COMMAND BYTE
.
BLOCK READ FORMAT
S ADDRESS
WR ACK COMMAND ACK SR ADDRESS WR ACK ACK ACK ACK ACK P
10h
SLAVE ADDRESS:
EQUIVALENT TO CHIP-
SELECT LINE OF A 3-
WIRE INTERFACE
SLAVE ADDRESS:
EQUIVALENT TO CHIP-
SELECT LINE OF A 3-
WIRE INTERFACE
SLAVE ADDRESS:
EQUIVALENT TO CHIP-
SELECT LINE OF A 3-
WIRE INTERFACE
COMMAND BYTE:
PREPARES DEVICE
FOR BLOCK
OPERATION
SLAVE ADDRESS:
EQUIVALENT TO CHIP-
SELECT LINE OF A 3-
WIRE INTERFACE
SLAVE ADDRESS:
EQUIVALENT TO CHIP-
SELECT LINE OF A 3-
WIRE INTERFACE
SLAVE ADDRESS:
EQUIVALENT TO CHIP-
SELECT LINE OF A 3-
WIRE INTERFACE
.
S ADDRESS
WR ACK COMMAND ACK DATA ACK P
7 BITS 8 BITS
8 BITS
8 BITS8 BITS8 BITS
8 BITS8 BITS8 BITS8 BITS
8 BITS
7 BITS
7 BITS 7 BITS
8 BITS
COMMAND BYTE:
SELECTS REGISTER YOU
ARE WRITING TO
1
0
0
0
10
DATA BYTE: DATA GOES INTO THE
REGISTER SET BY THE COMMAND
BYTE IF THE COMMAND IS BELOW
50h. IF THE COMMAND is 80h,
81h, or 82h, THE DATA BYTE PRESETS
THE LSB OF AN EEPROM ADDRESS.
S = START CONDITON
P = STOP CONDITION
SHADED = SLAVE TRANSMISSION
SR = REPEATED START CONDTION
Figure 11. SMBus/I
2
C Protocols
Read Byte
The read byte protocol allows the master device to
read the register or an EEPROM location (user or con-
figuration) content of the MAX6884/MAX6885 (see
Figure 11). The read byte procedure follows:
1) The master sends a START condition.
2) The master sends the 7-bit slave address and a
write bit (low).
3) The addressed slave asserts an ACK on the
data line.
4) The master sends 8 data bits.
5) The active slave asserts an ACK on the data line.
6) The master sends a repeated start condition.
7) The master sends the 7-bit slave ID plus a read
bit (high).
8) The addressed slave asserts an ACK on the
data line.
9) The slave sends 8 data bits.
10) The master asserts a NACK on the data line.
11) The master generates a STOP condition.