Datasheet

SMBus/I
2
C-Compatible Serial Interface
The MAX6884/MAX6885 feature an I
2
C/SMBus-compati-
ble 2-wire serial interface consisting of a serial data line
(SDA) and a serial clock line (SCL). SDA and SCL facili-
tate bidirectional communication between the
MAX6884/MAX6885 and the master device at clock
rates up to 400kHz. Figure 6 shows the 2-wire interface
timing diagram. The MAX6884/MAX6885 are transmit/
receive slave-only devices, relying upon a master
device to generate a clock signal. The master device
(typically a microcontroller) initiates data transfer on the
bus and generates SCL to permit that transfer.
A master device communicates to the MAX6884/
MAX6885 by transmitting the proper address followed by
command and/or data words. Each transmit sequence is
framed by a START (S) or REPEATED START (SR) condi-
tion and a STOP (P) condition. Each word transmitted
over the bus is 8 bits long and is always followed by an
acknowledge pulse.
SCL is a logic input, while SDA is an open-drain
input/output. SCL and SDA both require external pullup
resistors to generate the logic-high voltage. Use 4.7kΩ
resistors for most applications.
Bit Transfer
Each clock pulse transfers one data bit. The data on
SDA must remain stable while SCL is high (see Figure
7), otherwise the MAX6884/MAX6885 register a START
or STOP condition (see Figure 8) from the master. SDA
and SCL idle high when the bus is not busy.
MAX6884/MAX6885
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
26 ______________________________________________________________________________________
STOP
CONDITION
REPEATED START
CONDITION
START
CONDITION
t
HIGH
t
LOW
t
R
t
F
t
SU:DAT
t
SU:STA
t
SU:STO
t
HD:STA
t
BUF
t
HD:STA
t
HD:DAT
SCL
SDA
START
CONDITION
Figure 6. Serial Interface Timing
DATA LINE STABLE,
DATA VALID
SDA
SCL
CHANGE OF
DATA ALLOWED
Figure 7. Bit Transfer
PS
START
CONDITION
SDA
SCL
STOP
CONDITION
Figure 8. Start and Stop Conditions