Datasheet

Detailed Description
Many dual-supply processors or multivoltage boards
require one power supply to rise to the proper operat-
ing voltage before another supply is applied. Improper
sequencing can lead to chip latchup, incorrect device
initiation, or long-term reliability degradation. If the vari-
ous supply voltages are not locally generated (coming
from a main system bus, an externally purchased silver
box, or a nonsequenced power management chip),
power-on and power-off sequencing can be difficult to
control or predict. Supply loading can affect turn-
on/turn-off times from board to board.
The MAX6819/MAX6820 provide proper local voltage
sequencing in multisupply systems. The sequencers use
an external n-channel MOSFET to switch the secondary
supply to the load only when the primary supply is above
a desired operating voltage threshold. The n-channel
MOSFET operates in a default off mode when the primary
supply is below the desired threshold or if neither supply
exceeds the sequencer’s UVLO level.
When the primary supply voltage is above the set
threshold, the external MOSFET is driven on. An inter-
nal charge pump fully enhances the external MOSFET
by providing a gate-to-source voltage (V
GS
) of +5.5V
(typ). The charge pump fully enhances the MOSFET to
yield a low drain-to-source impedance (R
DS(ON)
) for
reduced switch voltage drop. The MOSFET is never dri-
ven on unless the sequencer can provide a minimum
V
GS
enhancement, ensuring that the switch MOSFET
never operates in its higher impedance linear range.
Either supply may act as the primary source, regard-
less of the voltage level, provided that V
CC1
or V
CC2
is
greater than 2.125V (Figure 1 and Figure 2).
MAX6819/MAX6820
SOT23 Power-Supply Sequencers
_______________________________________________________________________________________ 5
PIN
MAX6819
MAX6820
NAME
FUNCTION
11V
CC1
Supply Voltage 1. Either V
CC1
or V
CC2
must be greater than the UVLO to enable
external MOSFET drive.
22GND Ground
33SETV
Sequence Threshold Set. Connect to an external resistor-divider network to set the
V
CC1
threshold that enables GATE turn-on. The internal reference is 0.618V.
4—EN
Active-High Enable. GATE drive is enabled t
DELAY
after EN is driven high. GATE
drive is immediately disabled when EN is driven low. Connect to the higher of V
CC1
and V
CC2
if not used.
—4SETD
GATE Delay Set Input. Connect an external capacitor from SETD to GND to adjust
the delay from SETV > V
TH
to GATE turn-on. t
DELAY
(s) = 2.484 x 10
6
x C
SET
(F).
55GATE
GATE Drive Output. GATE drives an external n-channel MOSFET to connect V
CC2
to
the load. GATE drive enables t
DELAY
after SETV exceeds V
TH
and ENABLE is driven
high. GATE drive is immediately disabled when SETV drops below V
TH
or ENABLE is
driven low. When enabled, an internal charge pump drives GATE to V
CC2
+ 5.5V to
fully enhance the external n-channel MOSFET.
66V
CC2
Supply Voltage 2. Either V
CC1
or V
CC2
must be greater than the UVLO to enable
external MOSFET drive.
Pin Description
SETV
( ) FOR MAX6820 ONLY
V
CC2
V
CC2
OUT
0.62V
V
CC1
GND
SEQUENCE
DELAY/
LOGIC
GATE
EN (SETD)
GATE DRIVE
CHARGE PUMP
UVLO
Figure 1. Functional Diagram