Datasheet

Detailed Description
The MAX6746–MAX6753 assert a reset signal whenever
the V
CC
supply voltage or RESET IN falls below its reset
threshold. The reset output remains asserted for the reset
timeout period after V
CC
and RESET IN rise above its
respective reset threshold. A watchdog timer triggers a
reset pulse whenever a watchdog fault occurs.
The reset and watchdog delays are adjustable with
external capacitors. The MAX6746–MAX6751 contain a
watchdog select input that extends the watchdog timeout
period to 128x.
The MAX6752 and MAX6753 have a sophisticated watch-
dog timer that detects when the processor is running out-
side an expected window of operation. The watchdog sig-
nals a fault when the input pulses arrive too early (faster
that the selected t
WD1
timeout period) or too late (slower
than the selected t
WD2
timeout period) (see Figure 1).
Reset Output
The reset output is typically connected to the reset input
of a μP. A μP’s reset input starts or restarts the μP in a
known state. The MAX6746–MAX6753 μP supervisory
circuits provide the reset logic to prevent code-execution
errors during power-up, power-down, and brownout condi-
tions (see the Typical Operating Circuit). RESET changes
from high to low whenever the monitored voltage, RESET
IN and/or V
CC
drop below the reset threshold voltages.
Once V
RESET IN
and/or V
CC
exceeds its respective reset
threshold voltage(s), RESET remains low for the reset
timeout period, then goes high.
RESET is guaranteed to be in the correct logic state for
V
CC
greater than 1V. For applications requiring valid reset
logic when V
CC
is less than 1V, see the Ensuring a Valid
RESET Output Down to V
CC
= 0V section.
RESET IN Threshold
The MAX6748–MAX6751 monitor the voltage on RESET
IN using an adjustable reset threshold (V
RESET IN
) set
with an external resistor voltage-divider (Figure 2). Use
the following formula to calculate the externally monitored
voltage (V
MON_TH
):
V
MON_TH
= V
RESET IN
x (R1 + R2)/R2
Figure 1. MAX6752/MAX6753 Detailed Watchdog Input Timing Relationship
Figure 2. Calculating the Monitored Threshold Voltage
(V
MON_TH
)
WDI CONDITION 1
WDI CONDITION 2
WDI CONDITION 3
GUARANTEED TO
NOT ASSERT
RESET
GUARANTEED TO
ASSERT
RESET
t
WD1
(MIN) t
WD1
(MAX)
*UNDETERMINED *UNDETERMINED
FAST FAULT
NORMAL OPERATION
SLOW FAULT
*UNDETERMINED STATES MAY OR MAY NOT GENERATE A FAULT CONDITION
GUARANTEED
TO ASSERT
RESET
t
WD2
(MIN) t
WD2
(MAX)
MAX6748
MAX6749
MAX6750
MAX6751
RESET IN
GND
V
CC
V
CC
V
MON_TH
V
MON_TH
= 1.235 x (R1 + R2) / R2
R1
R2
MAX6746–MAX6753 μP Reset Circuits with Capacitor-Adjustable
Reset/Watchdog Timeout Delay
www.maximintegrated.com
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