Datasheet

(V
CC
= +1.2V to +5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise specified. Typical values are at V
CC
= +5V and T
A
= +25°C.) (Note 1)
Note 1: Production testing done at T
A
= +25°C. Over temperature limits are guaranteed by design.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Fast Watchdog Timeout Period,
SET Ratio = 64,
(MAX6752/MAX6753)
t
WD1
C
SWT
= 1500pF 11.38 15.18 18.98
ms
C
SWT
= 100pF 1.01
Fast Watchdog Minimum Period
(MAX6752/MAX6753)
2000 ns
SWT Ramp Current I
RAMP
V
SWT
= 0 to 1.23V, V
CC
= 1.6V to 5V 200 250 300 nA
SWT Ramp Threshold V
RAMP
V
CC
= 1.6V to 5V (V
RAMP
rising) 1.173 1.235 1.297 V
RESET Output-Voltage Low
Open-Drain, Push-Pull
(Asserted)
V
OL
V
CC
≥ 1.0V, I
SINK
= 50µA 0.3
VV
CC
≥ 2.7V, I
SINK
= 1.2mA 0.3
V
CC
≥ 4.5V, I
SINK
= 3.2mA 0.4
RESET Output-Voltage High,
Push-Pull (Not Asserted)
V
OH
V
CC
≥ 1.8V, I
SOURCE
= 200µA 0.8 x V
CC
VV
CC
≥ 2.25V, I
SOURCE
= 500µA 0.8 x V
CC
V
CC
≥ 4.5V, I
SOURCE
= 800µA 0.8 x V
CC
RESET Output Leakage Current,
Open Drain
I
LKG
V
CC
> V
TH
, reset not asserted,
V
RESET
= 5.5V
1.0 µA
DIGITAL INPUTS (MR, SET0, SET1, WDI, WDS)
Input Logic Levels
V
IL
V
CC
≥ 4.0V
0.8
V
V
IH
2.4
V
IL
V
CC
< 4.0V 0.3 x V
CC
V
IH
0.7 x V
CC
MR Minimum Pulse Width 1 µs
MR Glitch Rejection 100 ns
MR-to-RESET Delay 200 ns
MR Pullup Resistance Pullup to V
CC
12 20 28 kΩ
WDI Minimum Pulse Width 300 ns
RESET IN
RESET IN Threshold V
RESET IN
T
A
= -40°C to +125°C 1.216 1.235 1.254 V
RESET IN Leakage Current I
RESET IN
-50 ±1 +50 nA
RESET IN to RESET Delay RESET IN falling at 1mV/µs 20 µs
MAX6746–MAX6753 μP Reset Circuits with Capacitor-Adjustable
Reset/Watchdog Timeout Delay
www.maximintegrated.com
Maxim Integrated │ 3
Electrical Characteristics (continued)