Datasheet

RESET, strobe WDI between t
WD1(max)
and t
WD2(min)
.
The watchdog timer is cleared when RESET is asserted
or after a falling transition on WDI, or after a state
change on SET0 or SET1. Disable the watchdog timer by
connecting SET0 high and SET1 low.
Applications Information
Selecting Reset/Watchdog
Timeout Capacitor
The reset timeout period is adjustable to accommodate a
variety of μP applications. Adjust the reset timeout period
(t
RP
) by connecting a capacitor (C
SRT
) between SRT and
ground. Calculate the reset timeout capacitor as folllows:
C
SRT
= t
RP
/(5.06 x 10
6
)
with t
RP
in seconds and C
SRT
in Farads.
The watchdog timeout period is adjustable to
accommodate a variety of μP applications. With this
feature, the watchdog timeout can be optimized for soft-
ware execution. The programmer can determine how
often the watchdog timer should be serviced. Adjust
the watchdog timeout period (t
WD
) by connecting a
specific value capacitor (C
SWT
) between SWT and GND.
For normal mode operation, calculate the watchdog
timeout capacitor as follows:
C
SWT
= t
WD
/(5.06 x 106)
with t
WD
in seconds and C
SWT
in Farads.
For the MAX6752 and MAX6753 windowed watchdog
function, calculate the slow watchdog period, t
WD2
as
follows:
t
WD2
= 0.65 x 10
9
x C
SWT
C
SRT
and C
SWT
must be a low-leakage (< 10nA) type
capacitor. Ceramic capacitors are recommended.
Transient Immunity
In addition to issuing a reset to the μP during power-up,
power-down, and brownout conditions, these supervisors
are relatively immune to short-duration supply transients
(glitches). The Maximum Transient Duration vs. Reset
Threshold Overdrive graph in the Typical Operating
Characteristics shows this relationship.
The area below the curves of the graph is the region in
which these devices typically do not generate a reset pulse.
This graph was generated using a falling pulse applied to
V
CC
, starting above the actual reset threshold (V
TH
) and
Figure 5. MAX6752/MAX6753 Window Watchdog Diagram
Figure 6. Interfacing to Other Voltage Levels
WDI
(a) FAST FAULT
(b) SLOW FAULT
WDI
RESET
(c) NORMAL OPERATION (NO PULSING, OUTPUT STAYS HIGH)
RESET
WDI
RESET
t
WDI
< t
WD1
(MIN)
t
WDI
> t
WD2
(MAX)
t
WD1
(MAX) < t
WDI
< t
WD2
(MIN)
MAX6747
MAX6749
MAX6451
MAX6753
GND
N
RESET
RESET
5V
V
CC
V
CC
GND
3.3V
µP
100kΩ
MAX6746–MAX6753 μP Reset Circuits with Capacitor-Adjustable
Reset/Watchdog Timeout Delay
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