Datasheet

MAX6469–MAX6484
300mA LDO Linear Regulators with Internal
Microprocessor Reset Circuit
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MAX6469/MAX6470/MAX6477/MAX6478 Pin Description
PIN BUMP
MAX6469/MAX6470 MAX6477/MAX6478
SOT23 TDFN-EP UCSP
NAME FUNCTION
1 1, 2 A1 IN Regulator Input. Bypass IN to GND with a 0.1µF capacitor.
2 3 A2 GND
Ground. This pin also functions as a heatsink. Solder to large pads or
the circuit-board ground plane to maximize thermal dissipation.
34 A3 SHDN Active-Low Shutdown Input. Connect SHDN to V
IN
for normal operation.
45 C3 RESET
Active-Low Reset Output. RESET remains low while V
OUT
is below the
reset threshold. RESET remains low for the duration of the reset timeout
period after the reset conditions are terminated. RESET is available in
open-drain and push-pull configurations.
5 6 C2 SET
Feedback Input for Externally Setting the Output Voltage. Connect SET
to GND to select the preset output voltage. Connect SET to an external
resistor-divider network for adjustable output operation.
6 7, 8 C1 OUT
Regulator Output. Bypass OUT to GND with a minimum 3.3µF low-ESR
capacitor.
—— — EP
Exposed Paddle (TDFN Only). EP is internally connected to GND.
Connect EP to the ground plane to provide a low thermal-resistance
path from the IC junction to the PCB. Do not use as the electrical
connection to GND.
MAX6471/MAX6472/MAX6479/MAX6480 Pin Description
PIN BUMP
MAX6471/MAX6472 MAX6479/MAX6480
SOT23 TDFN-EP UCSP
NAME FUNCTION
1 1, 2 A1 IN Regulator Input. Bypass IN to GND with a 0.1µF capacitor.
2 3 A2 GND
Ground. This pin also functions as a heatsink. Solder to large pads or
the circuit-board ground plane to maximize thermal dissipation.
34 A3 MR
Active-Low Manual Reset Input. The reset output is asserted while MR
is pulled low and remains asserted for the duration of the reset timeout
period after MR transitions from low to high. Leave MR unconnected or
connect to V
OUT
if not used. MR has an internal pullup resistor of 40kΩ
(typ) to V
OUT
.
45 C3 RESET
Active-Low Reset Output. RESET remains low while V
OUT
is below the
reset threshold or while MR is held low. RESET remains low for the
duration of the reset timeout period after the reset conditions are
terminated. RESET is available in open-drain and push-pull
configurations.
5 6 C2 SET
Feedback Input for Externally Setting the Output Voltage. Connect SET
to GND to select the preset output voltage. Connect SET to an external
resistor-divider network for adjustable output operation.
6 7, 8 C1 OUT
Regulator Output. Bypass OUT to GND with a minimum 3.3µF low-ESR
capacitor.
—— — EP
Exposed Paddle (TDFN Only). EP is internally connected to GND.
Connect EP to the ground plane to provide a low thermal-resistance
path from the IC junction to the PCB. Do not use as the electrical
connection to GND.