Datasheet

Detailed Description
Reset Output
The reset output is typically connected to the reset
input of a microprocessor (µP). A µP’s reset input starts
or restarts the µP in a known state. The MAX6443–
MAX6452 µP supervisory circuits provide the reset
logic to prevent code-execution errors during power-
up, power-down and brownout conditions (see the
Typical Operating Circuit).
RESET changes from high to low whenever the moni-
tored voltages (RSTIN or V
CC
) drop below the reset
threshold voltages. Once V
RSTIN
and V
CC
exceed their
respective reset threshold voltages, RESET remains low
for the reset timeout period and then goes high. RESET
is one-shot pulsed whenever selected manual reset
inputs are asserted. RESET stays asserted for the nor-
mal reset timeout period (140ms min).
RESET is guaranteed to be in the proper output logic
state for V
CC
inputs ≥ 1V. For applications requiring valid
reset logic when V
CC
is less than 1V, see the Ensuring a
Valid RESET Output Down to V
CC
= 0V section.
PIN
NAME FUNCTION
MAX6443
MAX6444
MAX6445
MAX6446
MAX6447
MAX6448
MAX6449
MAX6450
MAX6451
MAX6452
1 2 2 2 2 GND Ground
2 1 1 1 1 RESET
Active-Low Push-Pull or Open-Drain Output. RESET
changes from high to low when V
CC
or RSTIN drops below
its selected reset threshold and remains low for the 210ms
reset timeout period after all monitored power-supply inputs
exceed their selected reset thresholds. RESET is one-shot
pulsed low for the reset timeout period (140ms min) after
selected manual reset inputs are asserted longer than the
specified setup period. For the open-drain output, use a
minimum 20kW pullup resistor to V
CC
.
3 — 3 — 3
MR1
Manual Reset Input, Active Low. Internal 50kW pullup to
V
CC.
Pull MR1 low for the typical input pulse width (t
MR
)
to one-shot pulse RESET for the reset timeout period.
— 3 — 3 —
Manual Reset Input, Active Low. Pull both MR1 and
MR2 low for the typical input pulse width (t
MR
) to one-
shot pulse RESET for the reset timeout period.
4 4 4 4 4 V
CC
V
CC
Voltage Input. Power supply and input for the
primary microprocessor voltage reset monitor.
— 5 — 6 — MR2
Manual Reset Input, Active Low. Internal 50kW pullup to
V
CC
. Pull both MR1 and MR2 low for the typical input
pulse width (t
MR
) to one-shot pulse RESET for the reset
timeout period.
— — 5 — 6 MR2
Manual Reset Input. Pull the MR2 high to immediately
one-shot pulse RESET for the reset timeout period.
— — — 5 5 RSTIN
Reset Input. High-impedance input to the adjustable
reset comparator. Connect RSTIN to the center point
of an external resistor-divider to set the threshold of the
externally monitored voltage.
MAX6443–MAX6452 µP Reset Circuits with Long Manual Reset
Setup Period
www.maximintegrated.com
Maxim Integrated │ 5
Pin Description