Datasheet

During the normal operating mode, the supervisor issues
a reset pulse for the reset timeout period (140ms min) if
the μP does not update the WDI with a valid transition
(high to low or low to high) within the standard timeout
period (1.6s min).
After each reset event (V
CC
power-up, manual reset, or
watchdog reset), there is an initial watchdog startup time-
out period of 25.6s. The startup mode provides an extend-
ed period for the system to power up and fully initialize all
μP and system components before assuming responsibil-
ity for routine watchdog updates. The normal watchdog
timeout period (1.6s min) begins at the conclusion of the
startup timeout period or after the first transition on WDI
before the conclusion of the startup period (Figure 3).
Applications Information
Ensuring a Valid RESET Output
Down to V
CC
= 0
In some systems, it is necessary to ensure a valid reset
even if V
CC
falls to 0. In these applications, use the
circuit shown in Figure 4. Note that this configuration does
not work for the open-drain outputs of the MAX6352/
MAX6355/MAX6358.
Interfacing to μPs with
Bidirectional Reset Pins
Microprocessors with bidirectional reset pins contend with
the push-pull outputs of these devices. To prevent this,
connect a 4.7kΩ resistor between RESET and the μP’s
reset I/O port, as shown in Figure 5. Buffer RESET, as
shown in the figure, if this reset is used by other compo-
nents in the system.
Figure 3. Normal Watchdog Startup Sequence
Figure 4. Ensuring a Valid Reset Low to V
CC
1 and V
CC
2 = 0
Figure 5. Interfacing to μPs with Bidirectional Reset I/O
1.6s
MAX
t
WDI-NORMAL
1.6s MAX
t
WDI-STARTUP
25.6s MAX
V
TH
V
CC
WDI
RESET
140ms
V
CC
2 V
CC
1
GND
100kΩ
RST2
RST1
RST
MAX6351 MAX6356
MAX6353 MAX6357
MAX6354 MAX6359
MAX6360
V
CC
2
V
CC
1
BUFFERED RESET TO OTHER SYSTEM COMPONENTS
4.7kΩ
GND
RESET
µP
GND
RST2
RST1
RST
V
CC
2
V
CC
2
V
CC
1
V
CC
1
MAX6351–MAX6360
MAX6351–MAX6360 Dual/Triple-Voltage
μP Supervisory Circuits
www.maximintegrated.com
Maxim Integrated │ 8