Datasheet

7Maxim Integrated
MAX5988A/MAX5988B
IEEE 802.3af-Compliant, High-Efficiency, Class 1/Class 2,
Powered Devices with Integrated DC-DC Converter
Figure 1. MAX5988A–MAX5988D Internal TVS Test Setup Figure 2. Effective Differential Resistance and Offset Current
Note 3: All devices are 100% production tested at T
A
= +25°C. Limits over temperature are guaranteed by design.
Note 4: The input offset current is illustrated in Figure 2.
Note 5: Effective differential input resistance is defined as the differential resistance between V
DD
and GND, see Figure 2.
Note 6: A 20V glitch on input voltage, which takes V
DD
below V
ON
shorter than or equal to t
OFF_DLY
does not cause the device to
exit power-on mode.
Note 7: The WAD detection rising and falling thresholds control the isolation power MOS transistor. To turn the DC-DC on in WAD
mode, the WAD must be detected and the V
DD
must be within the V
DD
voltage range.
Note 8 Referred to feedback regulation voltage.
Note 9: Referred to LDO feedback regulation voltage.
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 48V, R
SIG
= 24.9kω, LED, V
CC
, SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND,
C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), V
FB
= V
AUX
= 0V, LX unconnected, CLASS2 = 0V, MPS = 0V. All voltages are refer-
enced to GND, unless otherwise noted. T
A
= T
J
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
V
LDO_FB
Threshold for RESET
Assertion
V
LDO_FB-OKF
V
LDO_FB
falling, LDO_FB = V
DRV
(Note 9)
90 %
V
LDO_FB
Threshold for RESET
Deassertion
V
FB
rising 95 %
RESET Deassertion Delay 4.8 ms
EVALUATION
BOARD
1ms/10ms/100ms
R
TEST
MAX5988A
100V
I
IN
I
INi + 1
I
INi
I
OFFSET
dR
i
1VV
INi
V
INi + 1
I
OFFSET
= I
INi
-
V
INi
dR
i
dR
i
=
(V
INi + 1
- V
INi
)
=
1V
(I
INi + 1
- I
INi
) (I
INi + 1
- I
INi
)
V
IN