Datasheet
IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated 70W High-Power MOSFET
MAX5982A/MAX5982B/MAX5982C
4 ______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
IN
= (V
DD
- V
SS
) = 48V, R
DET
= 24.9kω, R
CLS
= 615ω, and R
SL
= 60.4kω. RTN, WAD, PG, 2EC, WK, and ULP unconnected, all
voltages are referenced to V
SS,
unless otherwise noted. T
A
= T
J
= -40NC to +85NC, unless otherwise noted. Typical values are at
T
A
= +25NC.) (Note 3)
Note 3:
All devices are 100% production tested at T
A
= +25NC. Limits over temperature are guaranteed by design.
Note 4: The input offset current is illustrated in Figure 1.
Note 5:
Effective differential input resistance is defined as the differential resistance between V
DD
and V
SS
. See Figure 1.
Note 6: Classification current is turned off whenever the device is in power mode.
Note 7: UVLO hysteresis is guaranteed by design, not production tested.
Note 8:
A 20V glitch on input voltage, which takes V
DD
below V
ON
shorter than or equal to t
OFF_DLY
does not cause the
MAX5982A/MAX5982B/MAX5982C to exit power-on mode.
Note 9: Maximum current limit during normal operation is guaranteed by design; not production tested.
Note 10: In power mode, current-limit foldback is used to reduce the power dissipation in the isolation MOSFET during an
overload condition across V
DD
and RTN.
Figure 1. Effective Differential Input Resistance/Offset Current
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LED Current Programmable
Range
10 20 mA
LED Current with Grounded SL V
SL
= 0V 20.5 24.5 28.5 mA
LED Current Frequency f
ILED
Normal and ultra-low-power sleep modes 250 Hz
LED Current Duty Cycle D
ILED
Normal and ultra-low-power sleep modes 25 %
V
DD
Current Amplitude I
VDD
Normal sleep mode, V
LED
= 3.5V 10 11 12.2 mA
Internal Current Duty Cycle D
IVDD
Normal and ultra-low-power sleep modes 75 %
Internal Current Enable Time t
MPS
Ultra-low-power sleep mode 80 84 88 ms
Internal Current Disable Time t
MPDO
Ultra-low-power sleep mode 220 228 236 ms
SL Delay Time t
SL
Time V
SL
must remain below the SL logic
threshold to enter sleep and ultra-low-
power modes (MAX5982A)
5.4 6.0 6.6 s
THERMAL SHUTDOWN
Thermal-Shutdown Threshold T
SD
T
J
rising +150 NC
Thermal-Shutdown Hysteresis T
J
falling 30 NC
I
IN
I
INi + 1
I
INi
I
OFFSET
dR
i
1VV
INi
V
INi + 1
I
OFFSET
= I
INi
-
V
INi
dR
i
dR
i
=
(V
INi + 1
- V
INi
)
=
1V
(I
INi + 1
- I
INi
)
(I
INi + 1
- I
INi
)
V
IN