Datasheet
MAX5965A/MAX5965B
High-Power, Quad, Monolithic, PSE Controllers
for Power over Ethernet
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Pin Description
PIN NAME FUNCTION
1 RESET
Hardware Reset. Pull RESET low for at least 300µs to reset the device. All internal registers reset to their
default value. The address (A0–A3), and AUTO and MIDSPAN input-logic levels latch on during low-to-
high transition of RESET. RESET is internally pulled up to V
DD
with a 50kΩ resistor.
2 MIDSPAN
Midspan Mode Input. An internal 50kΩ pulldown resistor to DGND sets the default mode to endpoint PSE
operation (power-over-signal pairs). Pull MIDSPAN to V
DIG
to set midspan operation. The MIDSPAN value
latches after the device is powered up or reset (see the PD Detection section).
3 INT
Open-Drain Interrupt Output. INT goes low whenever a fault condition exists. Reset the fault condition
using software or by pulling RESET low (see the Interrupt section for more information about interrupt
management).
4 SCL Serial Interface Clock Line Input
5 SDAOUT
Serial Output Data Line. Connect the data line optocoupler input to SDAOUT (see the Typical Operating
Circuits). Connect SDAOUT to SDAIN if using a 2-wire, I
2
C-compatible system.
Pin Configuration
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
OSC
AUTO
OUT1
GATE1
SENSE1
OUT2
GATE4
GATE2
SENSE2
V
EE
OUT3
GATE3
SENSE3
OUT4
DET4
DET3
DET2
DET1
A0
A1
A2
A3
SDAIN
SDAOUT
SCL
MIDSPAN
SSOP
TOP VIEW
MAX5965A
MAX5965B
22
21
20
19
15
16
17
18
SENSE4
AGNDV
DD
DGND
RESET
INT
SHD1
SHD2
SHD3
SHD4
+