Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsPMICsPMIC - PoE controller SSOP 36 Controller (PSE)

General Description

The MAX5965A/MAX5965B are quad, monolithic, -48V

power controllers designed for use in IEEE

802.3af-com-

pliant/IEEE 802.3at-compatible power-sourcing equipment

(PSE). These devices provide powered device (PD) dis-

covery, classification, current limit, DC and AC load discon-

nect detections in compliance with the IEEE 802.3af

standard. The MAX5965A/MAX5965B are pin compatible

with the MAX5952/MAX5945/LTC4258/LTC4259A PSE

controllers and provide additional features.

The MAX5965A/MAX5965B feature a high-power mode

that provides up to 45W per port. The MAX5965A/

MAX5965B provide new Class 5 and 2-event classifica-

tion (Class 6) for detection and classification of high-

power PDs. The MAX5965A/MAX5965B provide

instantaneous readout of each port current through the

C interface. The MAX5965A/MAX5965B also provide

high-capacitance detection for legacy PDs.

These devices feature an I

C-compatible, 3-wire serial inter-

face, and are fully software configurable and programmable.

The class-overcurrent detection function enables system

power management to detect if a PD draws more than the

allowable current. The MAX5965A/MAX5965B’s extensive

programmability enhances system flexibility, enables field

diagnosis, and allows for uses in other applications.

The MAX5965A/MAX5965B provide four operating modes

to suit different system requirements. Auto mode allows

the devices to operate automatically without any software

supervision. Semi-automatic mode automatically detects

and classifies a device connected to a port after initial

software activation, but does not power up that port until

instructed to by software. Manual mode allows total soft-

ware control of the device and is useful for system diag-

nostics. Shutdown mode terminates all activities and

securely turns off power to the ports.

The MAX5965A/MAX5965B provide input undervoltage

lockout (UVLO), input undervoltage detection, a load-

stability safety check during detection, input overvolt-

age lockout, overtemperature detection, output voltage

slew-rate limit during startup, power-good status, and

fault status. The MAX5965A/MAX5965B’s programma-

bility includes startup timeout, overcurrent timeout, and

load-disconnect detection timeout.

The MAX5965A/MAX5965B are available in a 36-pin SSOP

package and are rated for both extended (-40°C to +85°C)

and upper commercial (0°C to +85°C) temperature ranges.

Applications

Power-Sourcing Equipment (PSE)

Switches/Routers

Midspan Power Injectors

Features

o IEEE 802.3af Compliant/IEEE 802.3at Compatible

o Instantaneous Readout of Port Current Through

C Interface

o High-Power Mode Enables Up to 45W Per Port

o High-Capacitance Detection for Legacy Devices

o Pin Compatible with MAX5952/MAX5945/

LTC4258/LTC4259A

o Four Independent Power-Switch Controllers

o PD Detection and Classification (Including 2-

Event Classification)

o Selectable Load-Stability Safety Check During

Detection

o Supports Both DC and AC Load Removal

Detections

o I

C-Compatible, 3-Wire Serial Interface

o Current Foldback and Duty-Cycle-Controlled

Current Limit

o Open-Drain INT Signal

o Direct Fast Shutdown Control Capability

o Special Class 5 Classification

MAX5965A/MAX5965B

High-Power, Quad, Monolithic, PSE Controllers

for Power over Ethernet

________________________________________________________________

Maxim Integrated Products

19-4593; Rev 3; 3/12

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

Pin Configuration appears at end of data sheet.

Ordering Information

PART TEMP RANGE PIN-PACKAGE

MAX5965AEAX+ -40°C to +85°C 36 SSOP

MAX5965AUAX+* 0°C to +85°C 36 SSOP

MAX5965BEAX+ -40°C to +85°C 36 SSOP

MAX5965BUAX+* 0°C to +85°C 36 SSOP

Denotes a lead(Pb)-free/RoHS-compliant package.

Future product—contact factory for availability.

IEEE is a registered service mark of the Institute of Electrical and Electronics Engineers, Inc.

Selector Guide

PART PIN-PACKAGE

AC DISCONNECT

FEATURE

MAX5965AEAX+ 36 SSOP No

MAX5965AUAX+ 36 SSOP No

MAX5965BEAX+ 36 SSOP Yes

MAX5965BUAX+ 36 SSOP Yes

Summary of content (54 pages)

PAGE 1
9-4593; Rev 3; 3/12 High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet The MAX5965A/MAX5965B are quad, monolithic, -48V power controllers designed for use in IEEE® 802.3af-compliant/IEEE 802.3at-compatible power-sourcing equipment (PSE). These devices provide powered device (PD) discovery, classification, current limit, DC and AC load disconnect detections in compliance with the IEEE 802.3af standard.
PAGE 2
MAX5965A/MAX5965B High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VEE, unless otherwise noted.) AGND, DGND, DET_, VDD, RESET, A3–A0, SHD_, OSC, SCL, SDAIN, AUTO .............................................-0.3V to +80V OUT_........................................................-12V to (AGND + 0.3V) GATE_ (internally clamped) (Note 1) ..................-0.3V to +11.4V SENSE_ .............................................................
PAGE 3
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet (VAGND = 32V to 60V, VEE = 0V, VDD to VDGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at VAGND = +48V, VDGND = +48V, VDD = (VDGND + 3.3V), TA = +25°C. Currents are positive when entering the pin and negative otherwise.
PAGE 4
MAX5965A/MAX5965B High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet ELECTRICAL CHARACTERISTICS (continued) (VAGND = 32V to 60V, VEE = 0V, VDD to VDGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at VAGND = +48V, VDGND = +48V, VDD = (VDGND + 3.3V), TA = +25°C. Currents are positive when entering the pin and negative otherwise.
PAGE 5
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet (VAGND = 32V to 60V, VEE = 0V, VDD to VDGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at VAGND = +48V, VDGND = +48V, VDD = (VDGND + 3.3V), TA = +25°C. Currents are positive when entering the pin and negative otherwise.
PAGE 6
MAX5965A/MAX5965B High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet ELECTRICAL CHARACTERISTICS (continued) (VAGND = 32V to 60V, VEE = 0V, VDD to VDGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at VAGND = +48V, VDGND = +48V, VDD = (VDGND + 3.3V), TA = +25°C. Currents are positive when entering the pin and negative otherwise.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.
PAGE 7
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet (VAGND = 32V to 60V, VEE = 0V, VDD to VDGND = +3.3V, all voltages are referenced to VEE, unless otherwise noted. Typical values are at VAGND = +48V, VDGND = +48V, VDD = (VDGND + 3.3V), TA = +25°C. Currents are positive when entering the pin and negative otherwise.) (Note 2) PARAMETER Differential Nonlinearity SYMBOL CONDITIONS MIN DNL TYP MAX UNITS 0.2 1.
PAGE 8
Typical Operating Characteristics (VEE = -48V, VDD = +3.3V, VAUTO = VAGND = VDGND = 0V, RESET = SHD_ = unconnected, RSENSE_ = 0.5Ω, IVEE = 00, ICUT = 000, TA = +25°C, all registers = default setting, unless otherwise noted.) 5.1 5.0 4.9 4.8 5.2 5.1 4.8 4.6 4.5 4.5 40 44 48 52 56 VEE = -48V 4.9 4.7 36 VEE = -60V 5.0 4.6 60 VDD = 3.6V 120 115 VDD = 3.3V 110 105 VDD = 2.
PAGE 9
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet FOLDBACK CURRENT-LIMIT THRESHOLD vs. OUTPUT VOLTAGE 200 150 100 ICUT = 001 400 350 300 250 200 ICUT = 001 150 100 50 50 0 0 0 10 20 30 40 50 6 MAX5965A toc11 MAX5965A toc10A 450 VSENSE_ - VEE (mV) 250 VSENSE_ - VEE (mV) 500 MAX5965A toc10 300 DC LOAD DISCONNECT THRESHOLD vs. TEMPERATURE DC LOAD DISCONNECT THRESHOLD (mV) FOLDBACK CURRENT-LIMIT THRESHOLD vs.
PAGE 10
MAX5965A/MAX5965B High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet Typical Operating Characteristics (continued) (VEE = -48V, VDD = +3.3V, VAUTO = VAGND = VDGND = 0V, RESET = SHD_ = unconnected, RSENSE_ = 0.5Ω, IVEE = 00, ICUT = 000, TA = +25°C, all registers = default setting, unless otherwise noted.
PAGE 11
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet STARTUP IN MIDSPAN MODE WITH VALID PD (25kI AND 0.
PAGE 12
MAX5965A/MAX5965B High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet Typical Operating Characteristics (continued) (VEE = -48V, VDD = +3.3V, VAUTO = VAGND = VDGND = 0V, RESET = SHD_ = unconnected, RSENSE_ = 0.5Ω, IVEE = 00, ICUT = 000, TA = +25°C, all registers = default setting, unless otherwise noted.
PAGE 13
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet TOP VIEW + 36 OSC RESET 1 MIDSPAN 2 35 AUTO INT 3 34 OUT1 SCL 4 33 GATE1 SDAOUT 5 32 SENSE1 SDAIN 6 A3 7 30 GATE2 A2 8 29 SENSE2 A1 9 28 VEE MAX5965A MAX5965B A0 10 31 OUT2 27 OUT3 DET1 11 26 GATE3 DET2 12 25 SENSE3 DET3 13 24 OUT4 DET4 14 23 GATE4 DGND 15 22 SENSE4 VDD 16 21 AGND SHD1 17 20 SHD4 SHD2 18 19 SHD3 SSOP Pin Description PIN NAME 1 RESET 2 MIDSPAN 3 INT 4 SCL 5 FUNCTIO
PAGE 14
MAX5965A/MAX5965B High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet Pin Description (continued) PIN NAME 6 SDAIN Serial Interface Input Data Line. Connect the data line optocoupler output to SDAIN (see the Typical Operating Circuits). Connect SDAIN to SDAOUT if using a 2-wire, I2C-compatible system. 7–10 A3–A0 Address Bits. A3–A0 form the lower part of the device’s address. Address inputs default high with an internal 50kΩ pullup resistor to VDD.
PAGE 15
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet VDD SCL SHD_ SDAIN SDAOUT OSC DGND CURRENT SENSING VOLTAGE PROBING AND CURRENT-LIMIT CONTROL OSCILLATOR MONITOR THREE-WIRE SERIAL PORT INTERFACE DET_ A0 DETECTION/ CLASSIFICATION SM A1 9-BIT ADC CONVERTER VOLTAGE SENSING OUT_ 10V ACD_ENABLE PORT STATE MACHINE (SM) A2 REGISTER FILE A3 50µA A=3 GATE_ AUTO PWR_EN_ MIDSPAN CENTRAL LOGIC UNIT (CLU) AC DISCONNECT SIGNAL (ACD) RESET REGISTER FILE INT DGND AC DETECTION* FA
PAGE 16
MAX5965A/MAX5965B High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet Detailed Description The MAX5965A/MAX5965B are quad -48V power controllers designed for use in IEEE 802.3af-compliant/IEEE 802.3at-compatible PSE. The devices provide PD discovery, classification, current limit, DC and AC load disconnect detections in compliance with the IEEE 802.3af standard.
PAGE 17
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet Automatic (Auto) Mode Enter automatic (auto) mode by forcing the AUTO input high prior to a reset, or by setting R12h[P_M1,P_M0] to [1,1] during normal operation (see Tables 16a and 16b). In auto mode, the MAX5965A/MAX5965B performs detection, classification, and power up the port automatically once a valid PD is detected at the port.
PAGE 18
MAX5965A/MAX5965B High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet A valid PD has a 25kΩ discovery signature characteristic as specified in the IEEE 802.3af/at standard. Table 1 shows the IEEE 802.3af/at specification for a PSE detecting a valid PD signature. See the Typical Operating Circuits and Figure 1a (Detection, Classification, and Power-Up Port Sequence).
PAGE 19
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet During the PD classification mode, the MAX5965A/ MAX5965B force a probe voltage (-18V) at DET_ and measure the current into DET_. The measured current determines the class of the PD. After each classification cycle, the device sets the CL_END_ bit (R04h/05h[7:4]) high and reports the classification results in the status registers R0Ch[6:4], R0Dh[6:4], R0Eh[6:4], and R0Fh[6:4].
PAGE 20
MAX5965A/MAX5965B High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet 80ms 0V 150ms 150ms 21.3ms tDETI tDETII tCLASS t 0V -4V -9V OUT_ -18V -48V Figure 1a. Detection, Classification, and Power-Up Port Sequence 80ms 0 150ms 150ms 21.3ms 21.3ms tDETI tDETII tCLASSI tCLASSII 8ms 21.3ms tCLASSIII 8ms 0V -4V -9V OUT_ -18V -48V Figure 1b.
PAGE 21
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet tPGOOD PGOOD_ ICUT Register and High-Power Mode Figure 2. PGOOD_ Timing Overcurrent Protection A sense resistor RS connected between SENSE_ and VEE monitors the load current. Under normal operating conditions, the voltage across RS (VRS) never exceeds the threshold V SU_LIM . If V RS exceeds V SU_LIM , an internal current-limiting circuit regulates the GATE_ voltage, limiting the current to ILIM = VSU_LIM/RS.
PAGE 22
MAX5965A/MAX5965B High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet Table 3.
PAGE 23
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet Hardware Shutdown SHD_ shuts down the respective ports without using the serial interface. Hardware shutdown offers an emergency turn-off feature that allows a fast disconnect of the power supply from the port. Pull SHD_ low to remove power. SHD_ also resets the corresponding events and status register bits. Interrupt The MAX5965A/MAX5965B contain an open-drain logic output (INT) that goes low when an interrupt condition exists.
PAGE 24
MAX5965A/MAX5965B High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet Watchdog I2C-Compatible Serial Interface The R1Eh and R1Fh registers control the watchdog operation. The watchdog function, when enabled, allows the MAX5965A/MAX5965B to gracefully take over control or securely shuts down the power to the ports in case of software/firmware crashes. Contact the factory for more details.
PAGE 25
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet Bit Transfer Each clock pulse transfers one data bit (Figure 7). The data on SDA must remain stable while SCL is high. Acknowledge The acknowledge bit is a clocked 9th bit (Figure 8) that the recipient uses to handshake receipt of each byte of data. Thus each byte effectively transferred requires 9 bits.
PAGE 26
MAX5965A/MAX5965B High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet Slave Address The MAX5965A/MAX5965B have a 7-bit long slave address (Figure 9). The bit following the 7-bit slave address (bit eight) is the R/W bit, which is low for a write command and high for a read command. 010 always represents the first 3 bits (MSBs) of the MAX5965A/MAX5965B slave address.
PAGE 27
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet Operation with Multiple Masters When the MAX5965A/MAX5965B operate on a 2-wire interface with multiple masters, a master reading the MAX5965A/MAX5965B should use repeated starts between the write which sets the MAX5965A/ MAX5965B’s address pointer, and the read(s) that take the data from the location(s).
PAGE 28
MAX5965A/MAX5965B High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet Register Map and Description The interrupt register (Table 6) summarizes the event register status and is used to send an interrupt signal (INT goes low) to the controller. Writing a 1 to R1Ah[7] clears all interrupt and events registers. A reset sets R00h to 00h. INT_EN (R17h[7]) is a global interrupt mask (Table 7). The MASK_ bits activate the corresponding interrupt bits in register R00h.
PAGE 29
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet actual level of the bits. The power event register has two addresses. When read through the R02h address, the content of the register is left unchanged. When read through the CoR R03h address, the register content is cleared. A reset sets R02h/R03h = 00h. Table 8.
PAGE 30
MAX5965A/MAX5965B High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet LD_DISC_ is set high whenever the corresponding port shuts down due to detection of load removal. IMAX_FLT_ is set high when the port shuts down due to an extended overcurrent event after a successful startup. A 1 in any of the LD_DISC_ bits forces R00h[2] to 1. A 1 in any of the IMAX_FLT_ bits forces R00h[5] to 1. As with any of the other events register, the fault event register has two addresses.
PAGE 31
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet OSC_FAIL is set to 1 whenever the amplitude of the oscillator signal at the OSC input falls below a level that might compromise the AC disconnect detection function. OSC_FAIL generates an interrupt only if at least one of the ACD_EN (R13h[7:4]) bits is set high. A thermal shutdown circuit monitors the temperature of the die and resets the MAX5965A/MAX5965B if the temperature exceeds +150°C.
PAGE 32
MAX5965A/MAX5965B High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet The port status register (Table 13a) records the results of the detection and classification at the end of each phase in three encoding bits each. R0Ch contains the detection and classification status of port 1. R0Dh corresponds to port 2, R0Eh corresponds to port 3, and R0Fh corresponds to port 4. Tables 13b and 13c show the detection/classification result decoding charts, respectively.
PAGE 33
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet PWR_EN_ is set to 1 when the port power is turned on. PWR_EN_ resets to 0 as soon as the port turns off. Any transition of PGOOD_ and PWR_EN_ bits set the corresponding bit in the power event registers R02h/R03h (Table 8). A reset sets R10h = 00h. Table 14.
PAGE 34
MAX5965A/MAX5965B High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet The MAX5965A/MAX5965B use 2 bits for each port to set the mode of operation. Set the modes according to Table 16a and 16b. A reset sets R12h = AAAAAAAAb where A represents the latched-in state of the AUTO input prior to the reset. Use software to change the mode of operation. Software resets of ports (RESET_P_ bit, Table 23) do not affect the mode register. Table 16a.
PAGE 35
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet When entering auto mode, R14h defaults to FFh. When entering semi or manual modes, R14h defaults to 00h. A reset or power-up sets R14h = AAAAAAAAb where A represents the latched-in state of the AUTO input prior to the reset. Table 18.
PAGE 36
MAX5965A/MAX5965B High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet TSTART[1,0] (Table 20a) programs the startup timers. Startup time is the time the port is allowed to be in current limit during startup. TFAULT[1,0] programs the fault time. Fault time is the time allowed for the port to be in current limit during normal operation. RSTR[1,0] programs the discharge rate of the TFAULT_ counter and effectively sets the time the port remains off after an overcurrent fault.
PAGE 37
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet be active before startup. For Classes 4, 5, and 6, the corresponding enable bit in register R15h must be set together with EN_HP_ALL. In any other cases, the current level defaults to Class 0. CL_DISC, together with EN_HP_CL_ (R15h[6:4]), EN_HP_ALL (R15h[7]), and ENx_CL6 (R1Ch[7:4]) are used to program the high-power mode. See Table 3 for details. Setting OUT_ISO high (Table 21), forces DET_ to a high-impedance state.
PAGE 38
MAX5965A/MAX5965B High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet Writing a 1 to CLR_INT (Table 23) clears all the event registers and the corresponding interrupt bits in register R00h. Writing a 1 to RESET_P_ turns off power to the corresponding port and resets only the status and event registers of that port. After execution, the bits reset to 0. Writing a 1 to RESET_IC causes a global software reset, after which the register map is set back to its reset state.
PAGE 39
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet Enable the SMODE function (Table 25) by setting EN_WHDOG (R1Fh[7]) to 1. The SMODE_ bit goes high when the watchdog counter reaches zero and the port(s) switch over to hardware-controlled mode. SMODE_ also goes high each and every time the software tries to power on a port, but is denied since the port is in hardware mode. A reset sets R1Ch = 00h.
PAGE 40
MAX5965A/MAX5965B High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet Setting EN_WHDOG (Table 27) high activates the watchdog counter. When the counter reaches zero, the port switches to the hardware-controlled mode determined by the corresponding HWMODE_ bit. A low in HWMODE_ switches the port into shutdown by setting the bits in register R12h to 00. A high in HWMODE_ switches the port into auto mode by setting the bits in register R12h to 11.
PAGE 41
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet The IVEE bits enable the current-limit scaling (Table 30). This feature is used to reduce the current limit for systems running at higher voltage to maintain the desired output power. Table 31 sets the current-limit scaling register. A reset or power-up sets R29h = 00h. Table 29.
PAGE 42
MAX5965A/MAX5965B High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet The three ICUT_ bits (Tables 32a and 32b) allow programming of the current-limit and overcurrent thresholds in excess of the IEEE 802.3af standard limit. The MAX5965A/MAX5965B can automatically set the ICUT register or can be manually written to by the software (see Table 3). Class 1 and 2 limits can also be programmed by software independently from the classification status. See Table 3.
PAGE 43
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B Table 32c. ICUT Register Bit Values for Current-Limit Threshold ICUT_[2:0] (ADDRESS = 2Ah, 2Bh) SCALE FACTOR TYPICAL CURRENT-LIMIT THRESHOLD (mA) 000 1x 375 001 1.5x 563 010 1.75x 656 011 2x 750 100 2.25x 844 101 2.5x 938 110 0.3x Class 1 111 0.53x Class 2 Table 33a.
PAGE 44
MAX5965A/MAX5965B High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet Table 33b.
PAGE 45
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet ADDR REGISTER NAME R/W PORT BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET STATE INTERRUPTS 00h Interrupt RO G SUP_FLT TSTR_FLT IMAX_FLT CL_END DET_END LD_DISC PG_INT PEN_INT 0000,0000 01h Interrupt Mask R/W G MASK7 MASK6 MASK5 MASK4 MASK3 MASK2 MASK1 MASK0 AAA0,0A00 PG_CHG4 PG_CHG3 PG_CHG2 PG_CHG1 PWEN_ CHG4 PWEN_ CHG3 PWEN_ CHG2 PWEN_ CHG1 0000,0000 EVENTS 02h Power Event RO 4321
PAGE 46
MAX5965A/MAX5965B High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet Table 35.
PAGE 47
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet RJ–45 CONNECTOR 1 3 RX1+ RD1+ RX1- RD1- 24 1 22 2 1/2 OF 21 H2005A TX1+ 4 TD1+* 19 TX1- PHY 5 3 6 TD1- -48VOUT 0.1µF RXT1 23 75Ω 4 0.1µF 5 0.1µF TXCT1 75Ω 20 1000pF 250VAC 75Ω 75Ω 7 0.1µF 8 -48VRTN VCC (3.3V) VDD ISOLATION 1.8V TO 5V, (REF TO DGND) 3kΩ AGND VDD 180Ω A0 A1 A2 A3 1kΩ RESET INTERNAL 50kΩ PULLUP 3kΩ HPCL063L SERIAL INTERFACE VCCRTN 4.
PAGE 48
MAX5965A/MAX5965B High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet RJ–45 CONNECTOR 1 2 DATA 3 6 4 5 7 8 -48VOUT -48VRTN VCC (3.3V) VDD ISOLATION 1.8V TO 5V (REF TO DGND) 3kΩ AGND VDD 180Ω A0 A1 A2 A3 1kΩ RESET INTERNAL 50kΩ PULLUP 3kΩ HPCL063L SERIAL INTERFACE VCCRTN 4.
PAGE 49
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B R10 2Ω L1 68µH, DO3308P-683 R6 1Ω D1 DIODES INC.: B1100 C3 15nF C4 220µF Sanyo 6SVPA220MAA R5 1kΩ R1 2.61kΩ +3.3V 300mA C5 4.7µF Q2 MMBTA56 Q4 MMBTA56 GND +3.3V GND GND DRAIN 1 2 3 C6 0.47µF 100V 4 V+ MAX5020 VCC VDD NDRV FB GND SS_SHDN CS 8 R8 30Ω 7 6 Q3 MMBTA56 Q1 Si2328 DS C9 4.7nF SOURCE 5 C7 0.22µF C1 0.1µF C2 0.022µF GATE C8 2.2µF R4 1Ω -48V R9 1Ω R2 6.81kΩ R7 1.02kΩ R3 2.
PAGE 50
MAX5965A/MAX5965B High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet Component List for VDIG Supply DESIGNATION 50 DESCRIPTION DESIGNATION DESCRIPTION C1 0.1µF, 25V ceramic capacitor C2 0.022µF, 25V ceramic capacitor C3 15nF, 25V ceramic capacitor C4 220µF capacitor Sanyo 6SVPA220MAA C5 4.7µF, 16V ceramic capacitor C6 0.47µF, 100V ceramic capacitor R4, R6, R9 1Ω ±1% resistors C7 0.22µF, 16V ceramic capacitor R5 1kΩ ±1% resistor C8 2.
PAGE 51
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet -48V RTN OUTPUT TO PORT -48VRTN VCC (3.3V) ISOLATION VDD 1.8V TO 3.7V, (REF TO DGND) 3kΩ AGND VDD 180Ω A0 A1 A2 A3 1kΩ RESET 3kΩ INTERNAL 50kΩ PULLUP SERIAL INTERFACE VCCRTN HPCL063L 180Ω SDAOUT OPTIONAL BUFFER INT 3kΩ AUTO INTERNAL PULLDOWN (MANUAL MODE) MIDSPAN INTERNAL PULLDOWN (SIGNAL MODE) SDAIN MAX5965A MAX5965B HPCL063L SDA OPTIONAL BUFFER 180Ω 4.7kΩ OSC 3kΩ N.C.
PAGE 52
High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet MAX5965A/MAX5965B Typical Operating Circuits (continued) -48V RTN OUTPUT TO PORT -48VRTN VCC (3.3V) ISOLATION VDD 1.8V TO 3.7V, (REF TO DGND) 3kΩ AGND VDD 180Ω A0 A1 A2 A3 1kΩ RESET 3kΩ INTERNAL 50kΩ PULLUP SERIAL INTERFACE VCCRTN HPCL063L 180Ω SDAOUT OPTIONAL BUFFER INT 3kΩ AUTO INTERNAL PULLDOWN (MANUAL MODE) MIDSPAN INTERNAL PULLDOWN (SIGNAL MODE) SDAIN MAX5965A MAX5965B HPCL063L SDA OPTIONAL BUFFER 180Ω 4.
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High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet -48V RTN OUTPUT TO PORT -48VRTN VDD ISOLATION VCC (3.3V) 1.8V TO 3.7V, (REF TO DGND) 3kΩ AGND VDD 180Ω A0 A1 A2 A3 1kΩ RESET INTERNAL 50kΩ PULLUP 3kΩ HPCL063L SERIAL INTERFACE VCCRTN 4.7kΩ INT SDAOUT OPTIONAL BUFFER 180Ω SDAIN OPTIONAL BUFFER 180Ω INTERNAL PULLDOWN (MANUAL MODE) MIDSPAN INTERNAL PULLDOWN (SIGNAL MODE) MAX5965B HPCL063L SDA AUTO 3kΩ OSC SINE WAVE 100Hz ±10% PEAK AMPLITUDE 2.2V ±0.
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MAX5965A/MAX5965B High-Power, Quad, Monolithic, PSE Controllers for Power over Ethernet Revision History REVISION NUMBER REVISION DATE DESCRIPTION PAGES CHANGED 0 7/09 Initial release 1 1/10 Revised Features, Register Map and Description section, and Tables 32 and 37. 1, 37, 41, 45 — 2 5/11 Removed "pre-" from IEEE standard, updated Typical Operating Characteristics, and text throughout the data sheet. 1, 8–12, 15, 18, 22, 31, 40–47 3 3/12 Corrected power mode formula.