Datasheet
MAX5942A/MAX5942B
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
10 ______________________________________________________________________________________
MAX5942A/MAX5942B
Pin Description
PIN
NAME
FUNCTION
1V+
H i g h- V ol tag e S tar tup Inp ut. Refer enced to V - . C onnect d i r ectl y to an i np ut vol tag e r ang e b etw een 18V to 67V .
C onnects i nter nal l y to a hi g h- vol tag e l i near r eg ul ator that g ener ates V
C C
d ur i ng star tup .
2V
DD
Line Regulator Input. Referenced to V-. V
DD
is the input to the linear regulator that generates V
CC
. For
supply voltages less than 36V, connect V
DD
and V+ to the supply. For supply voltages greater than 36V,
V
DD
receives its power from the tertiary winding of the transformer and accepts voltages from 13V to 36V.
Bypass V
DD
to V- with a 4.7µF capacitor.
3FB
Fixed-Gain Inverting Amplifier Input. Referenced to V-. Connect a voltage-divider from the regulated output
to FB. The noninverting input of the amplifier is referenced to +2.4V
4
SS_SHDN
Soft-Start Timing Capacitor Connection. Referenced to V-. Ramp time to full current limit is approximately
0.45ms/nF. Bypass with a minimum 10nF capacitor to V-. A 2.4V reference voltage appears across the
capacitor. Disable the PWM controller by pulling SS_SHDN
below 0.25V.
5 UVLO
Undervoltage Lockout Programming Input for Power Mode. Referenced to V
EE
. When UVLO is above its
threshold, the device enters the power mode. Connect UVLO to V
EE
to use the default undervoltage lockout
threshold. Connect UVLO to an external resistor-divider to define a threshold externally. The series
resistance value of the external resistors must add to 25.5kΩ (±1%) and replaces the detection resistor. To
keep the device in undervoltage lockout, pull UVLO between V
TH,G,UVLO
and V
REF,UVLO
.
6 RCL Classification Setting. Referenced to V
EE
. Add a resistor from RCL to V
EE
to set a PD class (see Table 1).
7 GATE
Gate of Internal N-Channel Power MOSFET. Referenced to V
EE .
GATE sources 10µA when the device
enters the power mode. Connect an external 100V ceramic capacitor from GATE to V
OUT
to program the
inrush current. Pull GATE to V
EE
to turn off the internal MOSFET. The detection and classification functions
operate normally when GATE is pulled to V
EE
.
8V
EE
N e g a t i v e I n p u t P o w e r . S o u r ce o f th e i n te g r a t ed i s o l a t i o n N - c h a nn e l p ow e r M O S F E T . C o n n e ct V
E E
t o
- 4 8V .
9 OUT
Output Voltage. Referenced to V
EE
. Drain of the integrated isolation N-channel power MOSFET. Connect
OUT to V-.
10
PGOOD
Power-Good Indicator Output, Active High, Open Drain. PGOOD is referenced to OUT. PGOOD goes high
impedance when V
OUT
is within 1.2V of V
EE
and when GATE is 5V above V
EE
. Otherwise, PGOOD is pulled
to OUT (given that V
OUT
is at least 5V below GND).
11
PGOOD
Power-Good Indicator Output, Active Low, Open Drain. PGOOD is referenced to V
EE
. PGOOD is pulled to
V
EE
when V
OUT
is within 1.2V of V
EE
and when GATE is 5V above V
EE
. Otherwise, PGOOD goes high
impedance.
12 GND Ground. Referenced to V
EE
. GND is the positive input power.
13 CS
Current-Sense Input. Referenced to V-. Turns power switch off if V
CS
rises above 465mV for cycle-by-cycle
current limiting. CS is also the feedback for the current-mode controller. CS connects to the PWM controller
through a leading-edge blanking circuit.
14 V- Ground. V- is the ground terminal of the PWM controller.
15 NDRV Gate Drive. Referenced to V-. Drives a high-voltage external N-channel power MOSFET.
16 V
CC
Regulated IC Supply. Referenced to V-. Provides power for MAX5942_. V
CC
is regulated from V
DD
during
normal operation and from V+ during startup. Bypass V
CC
with a 10µF tantalum capacitor in parallel with a
0.1µF ceramic capacitor to V-.