Datasheet

MAX5938
-48V Hot-Swap Controller with V
IN
Step Immunity,
No R
SENSE
, and Overvoltage Protection
______________________________________________________________________________________ 23
∆V
CB
and ∆V
SC
and they represent the minimum V
OUT
excursion required to trip the respective fault.
R
STEP_MON
will typically be set to 100kΩ ±1%. This
gives a ∆V
STEP_MON
of 0.25V, a worst-case low of
0.13V, and a worst-case high of 0.37V. In finding τ
STEP
in the equation below, use ∆V
STEP_MON
= 0.37V to
ensure sufficient margin with worst-case I
STEP_OS
.
To set τ
STEP
to block all V
CB
and V
SC
faults for any
ramp rate, find the ratio of ∆V
STEP_MON
to ∆V
CB
and
choose τ
STEP
so:
τ
STEP
= 1.2 x τ
C
x ∆V
STEP_MON
/ ∆V
CB
and since R
STEP_MON
= 100kΩ:
C
STEP_MON
= τ
STEP
/ R
STEP_MON
= τ
STEP
/ 100kΩ
After the first-pass component selection, if sufficient
timing margin exists, it is possible (but not necessary)
to lower R
STEP
below 100kΩ to reduce the sensitivity of
STEP_MON to V
IN
noise.
Verification of the Step
Monitor Timing
It is prudent to verify conclusively that all circuit-breaker
and short-circuit faults will be blocked for all ramp
rates. To do this, some form of graphical analysis is
recommended but first, find the value of τ
L,eqv
of the
load by a series of ramp tests as indicated earlier.
These tests include evaluating the load with a series of
V
IN
ramps of increasing ramp rates and monitoring the
rate of rise of V
OUT
during the ramp. Each V
IN
ramp
should have a constant slope. The V
OUT
response data
must be taken only during the positive ramp. Data
taken after V
IN
has leveled off at the new higher value
must not be used.
Figure 21 shows the load in parallel with the load
capacitor, C
LOAD
, and the parallel connection in series
with the power MOSFET, which is fully enhanced with
V
GS
= 10V. The objective is to determine τ
L,eqv
from
the V
OUT
response.
Figure 22 shows the general response of V
OUT
to a V
IN
ramp over time t. Equation 1 gives the response of V
OUT
to a ramp of dV/dt. The product (dV/dt) x τ
C
=
∆V
OUT
(max) or the maximum V
OUT
voltage differential if
the V
IN
ramp were to continue indefinitely. The parame-
ter of interest is ∆V
OUT
due to the ramp dV/dt, thus it is
necessary to subtract the DC shift in V
OUT
due to the
load resistance. For some loads, which are relatively
independent of supply voltage, this may be insignificant.
V
OUT
(t) = V
OUT
(t) – R
DS(ON)
x I
LOAD
where I
LOAD
is a function of the V
OUT
level that should
be determined separately with DC tests.
Figure 21. V
IN
Ramp Test Of Load
L
EQU
R
EQV
C
LOAD
LOAD
LOAD CAPACITOR
WITH PARASITICS
V
IN
RAMP
V
IN
= GND = V
EE
10V
R
DS,ON
V
IN
Figure 22. General Response of V
OUT
to a V
IN
Ramp
dv
dt
τ
C
dv
dt
V
IN
V
OUT
.F
V
OUT
i
V
IN
RAMP
0
t1 t2 t3 t4
Figure 23. V
OUT
Response to V
IN
Ramp of 300V/ms
V
OUT
RESPONSE TO V
IN
RAMP OF 300V/ms
TIME (µs)
∆VOLTAGES (V)
764 52 31
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
0
08
A
B
d
VIN
dt
t
CB
t
SC
E
F
C
D
A = V
IN
(GND - V
EE
)
B = ∆V
STEP_MON
C = ∆V
OUT
D = ∆V
STEP,TH
E = ∆V
CB
F = ∆V
SC
t
STEP