Datasheet

MAX5895
16-Bit, 500Msps Interpolating and Modulating
Dual DAC with CMOS Inputs
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PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output High Voltage V
OH
200µA load
0.8 x
D V
D D 3 .3
V
Output Low Voltage V
OL
200µA load
0.2 x
D V
D D 3.3
V
Output Leakage Current Three-state 1 µA
Rise/Fall Time C
LOAD
= 10pF, 20% to 80% 1.5 ns
CLOCK INPUT (CLKP, CLKN)
Sine-wave input > 1.5
Differential Input Voltage Swing V
DIFF
Square-wave input > 0.5
V
P-P
Differential Input Slew Rate > 100 V/µs
Common-Mode Voltage V
COM
AC-coupled AV
CLK
/2 V
Input Resistance R
CLK
5kΩ
Input Capacitance C
CLK
3pF
Minimum Clock Duty Cycle 45 %
Maximum Clock Duty Cycle 55 %
CLKP/CLKN, DATACLK TIMING (Figure 4, Notes 7, 8)
CLK to DATACLK Delay t
D
DATACLK output mode, C
LOAD
= 10pF 6.2 ns
Capturing rising edge 1.0
Data Hold Time, DATACLK
Input/Output (Pin 14)
t
DH
Capturing falling edge 2.1
ns
Capturing rising edge 0.4
Data Setup Time, DATACLK
Input/Output (Pin 14)
t
DS
Capturing falling edge -0.7
ns
Capturing rising edge 1.0
Data Hold Time, DATACLK/B14
Input/Output (Pin 27)
t
DH
Capturing falling edge 2.3
ns
Capturing rising edge 0.2
Data Setup Time, DATACLK/B14
Input/Output (Pin 27)
t
DS
Capturing falling edge -0.4
ns
SERIAL-PORT INTERFACE TIMING (Figure 3, Note 7)
SCLK Frequency f
SCLK
10 MHz
CS Setup Time t
SS
2.5 ns
Input Hold Time t
SDH
0ns
Input Setup Time t
SDS
4.5 ns
Data Valid Duration t
SDV
6.5 16.5 ns
ELECTRICAL CHARACTERISTICS (continued)
(DV
DD1.8
= AV
DD1.8
= 1.8V, AV
CLK
= AV
DD3.3
= DV
DD3.3
= 3.3V, modulator off, 2x interpolation, DATACLK input mode, dual-port
mode, 50Ω double-terminated outputs, external reference at 1.25V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are
at T
A
= +25°C, unless otherwise noted.) (Note 2)