Datasheet

MAX5889
12-Bit, 600Msps, High-Dynamic-Performance
DAC with LVDS Inputs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= 3.3V, AV
DD1.8
= DV
DD1.8
= 1.8V, external reference V
REFIO
= 1.2V, output load 50Ω double-terminat-
ed, transformer-coupled output, I
OUT
= 20mA, T
A
= -40°C to +85°C, unless otherwise noted. Specifications at T
A
≥ +25°C are guar-
anteed by production testing. Specifications at T
A
< +25°C are guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Glitch Impulse Measured differentially 1
pV•s
I
OUT
= 2mA 30
Output Noise N
OUT
I
OUT
= 20mA 30
pA/√Hz
TIMING CHARACTERISTICS
Input Data Rate 600
MWps
Data Latency 5.5
Clock
cycles
Data to Clock Setup Time t
SETUP
Referenced to rising edge of clock (Note 4) -1.5
ns
Data to Clock Hold Time t
HOLD
Referenced to rising edge of clock (Note 4)
2.6 ns
Clock Frequency f
CLK
CLKP, CLKN 600
MHz
Minimum Clock Pulse-Width High
t
CH
CLKP, CLKN 0.6 ns
Minimum Clock Pulse-Width Low
t
CL
CLKP, CLKN 0.6 ns
Turn-On Time t
SHDN
External reference, PD falling edge to
output settle within 1%
350
µs
CMOS LOGIC INPUT (PD)
Input Logic High V
IH
0.7 x
DV
DD3.3
V
Input Logic Low V
IL
0.3 x
DV
DD3.3
V
Input Current I
IN
-10
±1.8 +10
µA
Input Capacitance C
IN
3pF
LVDS INPUTS
Differential Input High
V
IHLVDS
(Notes 6, 7, 8)
+100 +1000
mV
Differential Input Low
V
ILLVDS
(Notes 6, 7, 8)
-1000 -100
mV
Internal Common-Mode Bias
V
ICMLVDS
1.125 1.375
V
Differential Input Resistance
R
IDLVDS
110
Ω
Common-Mode Input Resistance
R
ICMLVDS
3.2 kΩ
Input Capacitance
C
INLVDS
3pF
DIFFERENTIAL CLOCK INPUTS (CLKP, CLKN)
Clock Common-Mode Voltage CLKP and CLKN are internally biased
AV
CLK
/ 2
V
Minimum Differential Input
Voltage Swing
0.5
V
P-P
Minimum Common-Mode Voltage
1V
Maximum Common-Mode
Voltage
1.9 V