Datasheet

MAX5874
14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
8 _______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1–7
A6, A5, A4,
A3, A2, A1, A0
Data Bits A6–A0. In dual-port mode, data is directed to the Q-DAC. In single-port mode, data bits
are not used. Connect bits A6–A0 to GND in single-port mode.
8, 9, 59, 60 N.C. No Connection. Leave floating or connect to GND.
10, 12, 13, 15,
20, 23, 26, 27,
30, 33, 36, 43
GND Converter Ground
11 DV
DD3.3
Digital Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1µF
capacitor to GND.
14, 21, 22, 31,
32
AV
DD3.3
Analog Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass each pin with
a 0.1µF capacitor to GND.
16 REFIO
Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a 1µF
capacitor to GND. REFIO can be driven with an external reference source. See Table1.
17 FSADJ
Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For a 20mA full-
scale output current, connect a 2kΩ resistor between FSADJ and DACREF. See Table1.
18 DACREF
Current-Set Resistor Return Path. For a 20mA full-scale output current, connect a 2kΩ resistor
between FSADJ and DACREF. Internally connected to GND. Do not use as an external ground
connection.
19, 34 AV
DD1.8
Analog Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass each pin with a
0.1µF capacitor to GND.
24 OUTQN Complementary Q-DAC Output. Negative terminal for current output.
25 OUTQP Q-DAC Output. Positive terminal for current output.
28 OUTIN Complementary I-DAC Output. Negative terminal for current output.
29 OUTIP I-DAC Output. Positive terminal for current output.
35 AV
CLK
Clock Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1µF
capacitor to GND.
37 CLKN
Complementary Converter Clock Input. Negative input terminal for differential converter clock.
Internally biased to AV
CLK
/ 2.
38 CLKP
Converter Clock Input. Positive input terminal for differential converter clock. Internally biased to
AV
CLK
/ 2.
39 TORB
Two’s-Complement/Binary Select Input. Set TORB to a CMOS-logic-high level to indicate a two’s-
complement input format. Set TORB to a CMOS-logic-low level to indicate a binary input format.
TORB has an internal pulldown resistor.
40 PD
Power-Down Input. Set PD to a CMOS-logic-high level to force the DAC into power-down mode.
Set PD to a CMOS-logic-low level for normal operation. PD has an internal pulldown resistor.
41 DORI
Dual (Parallel)/Single (Interleaved) Port Select Input. Set DORI high to configure as a dual-port
DAC. Set DORI low to configure as a single-port interleaved DAC. DORI has an internal pulldown
resistor.