Datasheet

MAX5874
14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
12 ______________________________________________________________________________________
Applications Information
CLK Interface
The MAX5874 features a flexible differential clock input
(CLKP, CLKN) with a separate supply (AV
CLK
) to
achieve optimum jitter performance. Use an ultra-low
jitter clock to achieve the required noise density. Clock
jitter must be less than 0.5ps
RMS
for meeting the speci-
fied noise density. For that reason, the CLKP/CLKN
input source must be designed carefully. The differen-
tial clock (CLKN and CLKP) input can be driven from a
single-ended or a differential clock source. Differential
clock drive is required to achieve the best dynamic
performance from the DAC. For single-ended opera-
tion, drive CLKP with a low-noise source and bypass
CLKN to GND with a 0.1µF capacitor.
Figure 5 shows a convenient and quick way to apply a
differential signal created from a single-ended source
(e.g., HP/AGILENT 8644B signal generator) and a wide-
band transformer. Alternatively, these inputs can be
driven from a CMOS-compatible clock source; however, it
is recommended to use sinewave or AC-coupled differ-
ential ECL/PECL drive for best dynamic performance.
t
S
t
H
t
PD
DATA13–DATA0, XOR
CLK
DAC OUTPUT
N - 1 N N + 1 N + 2
N - 5
N - 4
N - 3
N - 2
N - 6
SELIQ
CLK
DATA
IN
I0 Q2I2Q1I1 I3 Q3Q0
t
S
t
H
I OUT
Q OUT
t
PD
I - 5
I - 4 I - 2
I - 3
I - 6
Q - 6
Q - 5
Q - 4
Q - 3 Q - 2
(a) DUAL-PORT (PARALLEL) TIMING DIAGRAM
(b) SINGLE-PORT (INTERLEAVED) TIMING DIAGRAM
Figure 4. Timing Relationships Between Clock and Input Data for (a) Dual-Port (Parallel) Mode and (b) Single-Port (Interleaved) Mode