Datasheet

MAX5854
Dual, 10-Bit, 165Msps, Current-Output DAC
10 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 DA9/PD Channel A Input Data Bit 9 (MSB)/Power-Down
2
DA8/DACEN
Channel A Input Data Bit 8/DAC Enable Control
3 DA7/IDE Channel A Input Data Bit 7/Interleaved Data Enable
4
DA6/REN
Channel A Input Data Bit 6/Reference Enable. Setting REN = 0 enables the internal reference. Setting
REN = 1 disables the internal reference.
5 DA5/G3 Channel A Input Data Bit 5/Channel A Gain Adjustment Bit 3
6 DA4/G2 Channel A Input Data Bit 4/Channel A Gain Adjustment Bit 2
7 DA3/G1 Channel A Input Data Bit 3/Channel A Gain Adjustment Bit 1
8 DA2/G0 Channel A Input Data Bit 2/Channel A Gain Adjustment Bit 0
9 DA1 Channel A Input Data Bit 1
10 DA0 Channel A Input Data Bit 0 (LSB)
11 DB9 Channel B Input Data Bit 9 (MSB)
12 DB8 Channel B Input Data Bit 8
13 DB7 Channel B Input Data Bit 7
14 DB6 Channel B Input Data Bit 6
15 DB5 Channel B Input Data Bit 5
16 DV
DD
D i g i tal P ow er Inp ut. S ee the P ow er S up p l i es, Byp assi ng , D ecoup l i ng , and Layout secti on for m or e d etai l s.
17 DGND Digital Ground
18 DB4 Channel B Input Data Bit 4
19 DB3 Channel B Input Data Bit 3
20 DB2 Channel B Input Data Bit 2
21 DB1 Channel B Input Data Bit 1
22 DB0 Channel B Input Data Bit 0 (LSB)
23 CW Active-Low Control Word Write Pulse. The control word is latched on the rising edge of CW.
24 DCE
Active-Low Differential Clock Enable Input. Drive DCE low to enable the differential clock inputs
CLKXP and CLKXN. Drive DCE high to disable the differential clock inputs and enable the single-
ended CLK input.
25 CLKXP
Positive Differential Clock Input. With DCE = 0, CLKXP and CLKXN are enabled. With DCE = 1, CLKXP
and CLKXN are disabled. Connect CLKXP to CGND when the differential clock is disabled.
26 CLKXN
Negative Differential Clock Input. With DCE = 0, CLKXP and CLKXN are enabled. With DCE = 1, CLKXP
and CLKXN are disabled. Connect CLKXN to CV
DD
when the differential clock is disabled.
27, 30 CV
DD
Clock Power Input. See the Power Supplies, Bypassing, Decoupling, and Layout section for more
28 CLK
Single-Ended Clock Input/Output. With the differential clock disabled (DCE = 1), CLK becomes a
single-ended conversion clock input. With the differential clock enabled (DCE = 0), CLK is a single-
ended output that mirrors the differential clock inputs CLKXP and CLKXN. See the Clock Modes section
for more information on CLK.
29 CGND Clock Ground
31 REFO
Reference Input/Output. REFO serves as a reference input when the internal reference is disabled. If the
internal 1.24V reference is enabled, REFO serves as an output for the internal reference. When the
internal reference is enabled, bypass REFO to AGND with a 0.1µF capacitor