Datasheet

MAX5853
Dual, 10-Bit, 80Msps, Current-Output DAC
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I
FS
C
COMP
*
REFR
I
REF
REFO
MAX4040
1.24V
BANDGAP
REFERENCE
CURRENT-
SOURCE
ARRAY
*COMPENSATION CAPACITOR (C
COMP
≈ 100nF).
OPTIONAL EXTERNAL BUFFER
FOR HEAVIER LOADS
MAX5853
I
REF
=
V
REF
R
SET
R
SET
AGND
AGND
REN = 0
Figure 3. Setting I
FS
with the Internal 1.24V Reference and the
Control Amplifier
Internal Reference and Control Amplifier
The MAX5853 provides an integrated 50ppm/°C, 1.24V,
low-noise bandgap reference that can be disabled and
overridden with an external reference voltage. REFO
serves either as an external reference input or an inte-
grated reference output. If REN = 0, the internal refer-
ence is selected and REFO provides a 1.24V (50µA)
output. Buffer REFO with an external amplifier, when
driving a heavy load.
The MAX5853 also employs a control amplifier
designed to simultaneously regulate the full-scale out-
put current (I
FS
) for both outputs of the devices.
Calculate the output current as:
I
FS
= 32 ✕ I
REF
where I
REF
is the reference output current (I
REF
=
V
REFO
/ R
SET
) and I
FS
is the full-scale output current. R
SET
is the reference resistor that determines the amplifier out-
put current of the MAX5853 (Figure 3). This current is mir-
rored into the current-source array where I
FS
is equally
distributed between matched current segments and
summed to valid output current readings for the DACs.
External Reference
To disable the internal reference of the MAX5853, set
REN = 1. Apply a temperature-stable, external reference
to drive the REFO pin and set the full-scale output
(Figure 4). For improved accuracy and drift performance,
choose a fixed output voltage reference such as the
1.2V, 25ppm/°C MAX6520 bandgap reference.
Detailed Timing
The MAX5853 accepts an input data and DAC con-
version rate of up to 80Msps. The input latches on the
rising edge of the clock, whereas the output latches
on the following rising edge.
Figure 5 depicts the write cycle of the two DACs in non-
interleaved mode.
The MAX5853 can also operate in an interleaved data
mode. Programming the IDE bit with a high level activates
this mode (Tables 1 and 2). In interleaved mode, data for
both DAC channels is written through input port A.
Channel B data is written on the falling edge of the clock
signal and then channel A data is written on the following
rising edge of the clock signal. Both DAC outputs (chan-
nel A and B) are updated simultaneously on the next fol-
lowing rising edge of the clock. The interleaved data
mode is attractive for applications where lower data rates
are acceptable and interfacing on a single 10-bit bus is
desired (Figure 6).
AV
DD
EXTERNAL
1.2V
REFERENCE
MAX6520
AGND
0.1µF10µF
AV
DD
AGND
I
FS
REFR
I
REF
REFO
1.24V
BANDGAP
REFERENCE
CURRENT-
SOURCE
ARRAY
MAX5853
R
SET
AGND
REN = 1
Figure 4. MAX5853 with External Reference