Datasheet

MAX5853
Dual, 10-Bit, 80Msps, Current-Output DAC
12 ______________________________________________________________________________________
Device Power-Up and
States of Operation
At power-up, the MAX5853’s default configuration is inter-
nal reference, noninterleaved input mode with a gain of
0dB and a fully operational converter. In shutdown, the
MAX5853 consumes only 1µA of supply current, and in
standby the current consumption is 3.1mA. Wake-up time
from standby mode to normal operation is 3µs.
Clock Modes
The MAX5853 allows both single-ended CMOS and dif-
ferential clock mode operation, and supports update
rates of up to 80Msps. These modes are selected
through an active-low control line called DCE. In single-
ended clock mode (DCE = 1), the CLK pin functions as
an input, which accepts a user-provided single-ended
clock signal. Data is written to the converter on the rising
edge of the clock. The DAC outputs (previous data) are
updated simultaneously on the same edge.
If the DCE pin is pulled low, the MAX5853 operates in
differential clock mode. In this mode, the clock signal
has to be applied to the differential clock input pins
CLKXP/CLKXN. The differential input accepts an input
range of ≥0.5V
P-P
and a common-mode range of 1V to
(CV
DD
- 0.5V), making the part ideal for low-input ampli-
tude clock drives. CLKXP/CLKXN also help to minimize
the jitter, and allow the user to connect a crystal oscilla-
tor directly to the MAX5853.
The CLK pin now becomes an output, and provides a sin-
gle-ended replica of the differential clock signal, which
may be used to synchronize the input data. Data is writ-
ten to the device on the rising edge of the CLK signal.
CONTROL WORD
FUNCTION
PD Power-Down. The part enters power-down mode if PD = 1.
DACEN DAC Enable. When DACEN = 0 and PD = 0, the part enters standby mode.
IDE
Interleaved Data Mode. IDE = 1 enables the interleaved data mode. In this mode, digital data for both
channels is applied through channel A in a multiplexed fashion. Channel B data is written on the falling edge
of the clock signal and channel A data is written on the rising edge of the clock signal.
REN
Reference Enable Bit. REN = 0 activates the internal reference. REN = 1 disables the internal reference and
requires the user to apply an external reference between 0.1V to 1.32V.
G3 Bit 3 (MSB) of Gain Adjust Word
G2 Bit 2 of Gain Adjust Word
G1 Bit 1 of Gain Adjust Word
G0 Bit 0 (LSB) of Gain Adjust Word
Table 1. Control Word Format and Function
GAIN ADJUSTMENT ON
CHANNEL A (dB)
G3
G2
G1
G0
+0.4 0000
0 1000
-0.35 1111
Table 3. Gain Difference Setting
X = Don’t care.
MSB LSB
PD
DACEN
IDE REN G3 G2 G1 G0 X X
Table 2. Configuration Modes
MODE
PD DACEN IDE
REN
Normal operation;
noninterleaved inputs;
internal reference active
0100
Normal operation;
noninterleaved inputs;
internal reference disabled
0101
Normal operation;
interleaved inputs;
internal reference disabled
0111
Standby 0 0
X
X
Power-down 1 X
X
X
Power-up 0 1
X
X