Datasheet

JP1 (ADDR1) JP2 (ADDR0) A3 A2 A1 A0
1-2 (VDD) 1-2 (VDD) 1 1 1 1
1-2 (VDD) Open 1 1 1 0
1-2 (VDD) 2-3 (GND) 1 1 0 0
Open 1-2 (VDD) 1 0 1 1
Open Open 1 0 1 0
Open 2-3 (GND) 1 0 0 0
2-3 (GND) 1-2 (VDD) 0 0 1 1
2-3 (GND) Open 0 0 1 0
2-3 (GND) 2-3 (GND) 0 0 0 0
PIN SIGNAL DESCRIPTION
1 VDD Supply voltage
2
LDACEXT
Active-low asynchronous DAC load
input
3 GND Ground
4
CLR
Active-low asynchronous DAC clear
input
5 DAC7 DAC channel 7 voltage output
6 DAC6 DAC channel 6 voltage output
7 DAC5 DAC channel 5 voltage output
8 DAC4 DAC channel 4 voltage output
9 DAC3 DAC channel 3 voltage output
10 DAC2 DAC channel 2 voltage output
11 DAC1 DAC channel 1 voltage output
12 DAC0 DAC channel 0 voltage output
13 REF Reference voltage input/output
14 GND Ground
_________________________________________________________________ Maxim Integrated Products 3
MAX5825PMB1 Peripheral Module
Table 3. I
2
C Slave Address LSBs
Table 4. Connector J3 (External Interface)
I
2
C Addressing Options
The I
2
C slave address for the IC can be one of nine
different values, depending on the settings on jumpers
JP1 and JP2. Table 3 lists the settings of those jump-
ers and the corresponding values of the slave address
A[3:0]. Refer to the MAX5823/MAX5824/MAX5825 IC
data sheet for more information.
External Control Signals
The IC implements pins that allow asynchronously updat-
ing of all DAC channels simultaneously (LDAC) and
simultaneously clearing all DAC channels to their default
state (CLR). The CLR pin is only available through the
external J3 connector. The LDAC signal is available from
either the Pmod connector (J1) or the external connector
(J3). The default source for LDAC is the Pmod connector
(J1). To control LDAC from the external connector (J3),
modify the solder link on the back of the board (labeled
LK1). The user is cautioned to ensure that only one
source for this signal is selected at any given time.
The J3 connector provides the DAC output voltages and
the external control inputs. See Table 4.
Reset State (M/Z Pin)
The IC features a pin-selectable DAC reset state using
the M/Z input. Upon a power-on reset, all CODE and
DAC data registers are reset to zero scale (M/Z = GND)
or midscale (M/Z = VDD). The board is shipped with R11
installed (0I) and R10 not installed, which sets M/Z to
GND. To change to M/Z = VDD, remove R11 and install
a suitable pullup resistor for R10. Refer to the MAX5823/
MAX5824/MAX5825 IC data sheet for more information.
Software and FPGA Code
Example software and drivers are available that execute
directly without modification on several FPGA devel-
opment boards that support an integrated or synthe-
sized microprocessor. These boards include the Digilent
Nexys 3, Avnet LX9, and Avnet ZEDBoard, although
other platforms can be added over time. Maxim provides
complete Xilinx ISE projects containing HDL, Platform
Studio, and SDK projects. In addition, a synthesized bit
stream, ready for FPGA download, is provided for the
demonstration application.
The software project (for the SDK) contains several
source files intended to accelerate customer evalu-
ation and design. These include a base application
(maximModules.c) that demonstrates module function-
ality and uses an API interface (maximDeviceSpecific
Utilities.c) to set and access Maxim device functions
within a specific module.
The source code is written in standard ANSI C format, and
all API documentation including theory/operation, register
description, and function prototypes are documented in
the API interface file (maximDeviceSpecificUtilities.h & .c).
The complete software kit is available for download at
www.maxim-ic.com. Quick start instructions are also
available as a separate document.