Datasheet

MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I
2
C Interface
6Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 5.5V, V
DDIO
= 1.8V to 5.5V, V
GND
= 0V, C
L
= 200pF, R
L
= 2kI, T
A
= -40NC to +125NC, unless otherwise noted.)
(Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Low Voltage (Note 11) V
IL
(All inputs except
M/Z)
2.2V < V
DDIO
< 5.5V
0.3 x
V
DDIO
V
1.8V < V
DDIO
< 2.2V
0.2 x
V
DDIO
V
2.7V < V
DD
< 5.5V (for M/Z)
0.3 x
V
DD
Input Leakage Current I
IN
V
IN
= 0V or V
DDIO
, all inputs except M/Z
(Note 11)
Q0.1 Q1 FA
V
IN
= 0V or V
DD
, for M/Z (Note 11)
Input Capacitance (Note 10) C
IN
10 pF
Hysteresis Voltage V
H
0.15 V
ADDR_ Pullup/Pulldown Strength R
PU
, R
PD
(Note 12) 30 50 90 kI
DIGITAL OUTPUT (SDA, IRQ)
Output Low Voltage V
OL
I
SINK
= 3mA 0.2 V
Output Inactive Leakage I
OFF
IRQ only, see I
IN
for SDA Q0.1 Q1 FA
Output Inactive Capacitance C
OFF
IRQ only, see C
IN
for SDA 10 pF
WATCHDOG TIMER CHARACTERISTICS
Watchdog Timer Period t
WDOSC
V
DD
= 3V, T
A
= +25°C 0.95 1 1.05 ms
Watchdog Timer Period Supply
Drift
V
DD
= 2.7V to 5.5V, T
A
= +25°C 0.6 %/V
Watchdog Timer Period
Temperature Drift
V
DD
= 3V 0.0375 %/°C
I
2
C TIMING CHARACTERISTICS (SCL, SDA, LDAC, CLR)
SCL Clock Frequency f
SCL
400 kHz
Bus Free Time Between a STOP
and a START Condition
t
BUF
1.3 Fs
Hold Time Repeated for a START
Condition
t
HD;STA
0.6 Fs
SCL Pulse Width Low t
LOW
1.3 Fs
SCL Pulse Width High t
HIGH
0.6 Fs
Setup Time for Repeated START
Condition
t
SU;STA
0.6 Fs
Data Hold Time t
HD;DAT
0 900 ns
Data Setup Time t
SU;DAT
100 ns
SDA and SCL Receiving
Rise Time
t
R
20 +
C
B
/10
300 ns