Datasheet

MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I
2
C Interface
23Maxim Integrated
Table 4. I
2
C Commands Summary
COMMAND B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 DESCRIPTION
CONFIGURATION AND SOFTWARE COMMANDS WDOG 0 0 0 1 X X X` X TIMEOUT SELECTION[11:4]
TIMEOUT
SELECTION[3:0]
WD_MASK
Safety
Level
00: Low
01: Med
10: High
11: Max
X
Updates watchdog settings and safety levels
REF 0 0 1 0 0
REF
Pow-
er
0 =
DAC
1 =
ON
REF Mode
00 = EXT
01 = 2.5V 10 = 2.0V 11 = 4.1V
X X X X X X X X X X X X X X X
Sets the reference operating mode. REF Power (B18): 0 = Internal reference is only powered if at least one DAC is powered. 1 = Internal reference is always powered.
SW_GATE_CLR 0 0 1 1 0 0 0 0 1 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0
Removes any existing GATE condition
SW_GATE_SET 0 0 1 1 0 0 0 1 1 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0 Initiates a GATE condition
WD_REFRESH 0 0 1 1 0 0 1 0 1 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0 Refreshes the watchdog timer
WD_RESET 0 0 1 1 0 0 1 1 1 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0
Resets the watchdog timeout alarm status and refreshes the watchdog timer
SW_CLEAR 0 0 1 1 0 1 0 0 1 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0
Executes a software clear (all CODE and DAC registers cleared to their default values)
SW_RESET 0 0 1 1 0 1 0 1 1 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0
Executes a software reset (all CODE, DAC, and Control registers returned to their power-on reset values)
POWER 0 1 0 0 0 0 0 0
DAC 7
DAC 6
DAC 5
DAC 4
DAC 3
DAC 2
DAC 1
DAC 0
Power
Mode
00 =
Normal
01 = PD
1kW
10 = PD
100kW
11 = PD
Hi-Z
X X X X X X
Sets the Power mode of the selected DACs (DACs selected with a 1 in the corresponding DACn bit are updated, DACs with a 0 in the corresponding DACn bit are not impacted)
CONFIG 0 1 0 1 0 0 0 0
DAC 7
DAC 6
DAC 5
DAC 4
DAC 3
DAC 2
DAC 1
DAC 0
WDOG
Config-
uration
00: DIS
01: GATE
10: CLR
11: HOLD
GATE_ENB
LDAC_ENB
CLEAR_ENB
X X X
Configures selected DAC watchdog, GATE, LOAD, and CLEAR operations. DACs selected with a 1 in the corresponding DACn bit are updated, DACs with a 0 in the corresponding DACn bit are not impacted)