Datasheet

MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I
2
C Interface
21Maxim Integrated
Table 3. Format DAC Data Bit Positions
Figure 7. Interface Verification I
2
C Register Read Sequences
PART B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
MAX5823 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X
MAX5824 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X
MAX5825 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
SCL
AW 20 19 18 17 A16 15 14 13 12 11 10 9 A8
SDA
0 0 1 A3 A2 A1 A0 2223
7 6
5
4 3 2 1 A0
R
~A
POINTER UPDATED
(QUALIFIES FOR COMBINED READ BACK)
COMMAND EXECUTED
(QUALIFIES FOR INTERFACE READ BACK)
SCL
SDA
COMMAND EXECUTED
(QUALIFIES FOR INTERFACE READ BACK)
POINTER UPDATED
(QUALIFIES FOR COMBINED READ BACK)
21
AW20191817A16 15 14 13 12 11 10 9A8001A3A2A1A02223 7654321A021
START STOP
WRITE ADDRESS
BYTE #1: I
2
C SLAVE ADDRESS
WRITE COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
WRITE DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
WRITE DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
START STOP
WRITE ADDRESS
BYTE #1: I
2
C SLAVE ADDRESS
READ COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
READ DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
READ DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
START
REPEATED
START
WRITE ADDRESS
BYTE #1: I
2
C SLAVE ADDRESS
WRITE COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
WRITE DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
WRITE DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
STOP
WRITE ADDRESS
BYTE #1: I
2
C SLAVE ADDRESS
READ COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
READ DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
READ DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
ACK. GENERATED BY MAX5823/MAX5824/MAX5825 ACK. GENERATED BY I
2
C MASTER
A20191817A16 15 14 13 12 11 10 9A8001A3A2A1A02223 7654321021
AR20191817A16 15 14 13 12 11 10 9A8001A3A2A1A02223 7654321~A021
AA