Datasheet

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MAX5823/MAX5824/MAX5825

Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered

Output DACs with Internal Reference and I

C Interface

General Description

The MAX5823/MAX5824/MAX5825 8-channel, low-power,

8-/10-/12-bit, voltage-output digital-to-analog converters

(DACs) include output buffers and an internal 3ppm/°C

reference that is selectable to be 2.048V, 2.500V, or

4.096V. The MAX5823/MAX5824/MAX5825 accept a

wide supply voltage range of 2.7V to 5.5V with extremely

low power (6mW) consumption to accommodate most

low-voltage applications. A precision external reference

input allows rail-to-rail operation and presents a 100kI

(typ) load to an external reference.

The MAX5823/MAX5824/MAX5825 have an I

C-compatible,

2-wire interface that operates at clock rates up to

400kHz. The DAC output is buffered and has a low sup-

ply current of less than 250FA per channel and a low

offset error of Q0.5mV (typ). On power-up, the MAX5823/

MAX5824/MAX5825 reset the DAC outputs to zero or mid-

scale based on the status of M/Z logic input, providing

flexibility for a variety of control applications. The internal

reference is initially powered down to allow use of an

external reference. The MAX5823/MAX5824/MAX5825

allow simultaneous output updates using software LOAD

commands or the hardware load DAC logic input (LDAC).

The MAX5823/MAX5824/MAX5825 feature a watchdog

function which can be enabled to monitor the I/O inter-

face for activity and integrity.

A clear logic input (CLR) allows the contents of the CODE

and the DAC registers to be cleared asynchronously and

simultaneously sets the DAC outputs to the program-

mable default value. The MAX5823/MAX5824/MAX5825

are available in a 20-pin TSSOP and an ultra-small,

20-bump WLP package and are specified over the -40NC

to +125NC temperature range.

Applications

Programmable Voltage and Current Sources

Gain and Offset Adjustment

Automatic Tuning and Optical Control

Power Amplifier Control and Biasing

Process Control and Servo Loops

Portable Instrumentation

Benefits and Features

S Eight High-Accuracy DAC Channels

 12-Bit Accuracy Without Adjustment

±1 LSB INL Buffered Voltage Output

Guaranteed Monotonic Over All Operating

Conditions

Independent Mode Settings for Each DAC

S Three Precision Selectable Internal References

2.048V, 2.500V, or 4.096V

S Internal Output Buffer

Rail-to-Rail Operation with External Reference

 4.5µs Settling Time

 Outputs Directly Drive 2kI Loads

S Small 6.5mm x 4.4mm 20-Pin TSSOP or Ultra-

Small 2.5mm x 2.3mm 20-Bump WLP Package

S Wide 2.7V to 5.5V Supply Range

S Separate 1.8V to 5.5V V

DDIO

Power-Supply Input

S Fast 400kHz I

C-Compatible, 2-Wire Serial

Interface

S Pin-Selectable Power-On-Reset to Zero-Scale or

Midscale DAC Output

S LDAC and CLR For Asynchronous DAC Control

S Three Software-Selectable Power-Down Output

Impedances

1kI, 100kI, or High Impedance

19-6185; Rev 2; 2/13

Ordering Information appears at end of data sheet.

Functional Diagram

EVALUATION KIT AVAILABLE

ADDR0

SDA

SCL

OUT0

BUFFER

POR

WATCHDOG

TIMER

GND

DAC CONTROL LOGIC

POWER-DOWN

REF

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

DDIO

ADDR1

CLR

LDAC

IRQ

M/Z

C SERIAL

INTERFACE

1kI100kI

CODE LOAD

CLEAR/

RESET

(GATE/

CLEAR/

RESET)

CODE

DAC

LATCH

8-/10-/12-BIT

DAC

1 OF 8 DAC CHANNELS

INTERNAL REFERENCE/

EXTERNAL BUFFER

MAX5823

MAX5824

MAX5825

For pricing, delivery, and ordering information, please contact Maxim Direct

at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.

For related parts and recommended products to use with this part,

refer to: www.maximintegrated.com/MAX5823.related

Summary of content (35 pages)

PAGE 1
EVALUATION KIT AVAILABLE MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface General Description The MAX5823/MAX5824/MAX5825 8-channel, low-power, 8-/10-/12-bit, voltage-output digital-to-analog converters (DACs) include output buffers and an internal 3ppm/°C reference that is selectable to be 2.048V, 2.500V, or 4.096V. The MAX5823/MAX5824/MAX5825 accept a wide supply voltage range of 2.7V to 5.
PAGE 2
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface Absolute Maximum Ratings VDD, VDDIO to GND.................................................-0.3V to +6V OUT_, REF to GND.....0.3V to the lower of (VDD + 0.3V) and +6V SCL, SDA, IRQ, M/Z, LDAC, CLR to GND..............-0.3V to +6V ADDR_ to GND.............................................-0.3V to the lower of (VDDIO + 0.
PAGE 3
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface ELECTRICAL CHARACTERISTICS (continued) (VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DAC OUTPUT CHARACTERISTICS Output Voltage Range (Note 7) Load Regulation No load 0 VDD 2kI load to GND 0 VDD 0.2 2kI load to VDD 0.
PAGE 4
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface ELECTRICAL CHARACTERISTICS (continued) (VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted.
PAGE 5
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface ELECTRICAL CHARACTERISTICS (continued) (VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VDD V REFERENCE INPUT Reference Input Range 1.24 VREF Reference Input Current IREF Reference Input Impedance RREF VREF = VDD = 5.
PAGE 6
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface ELECTRICAL CHARACTERISTICS (continued) (VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted.) (Note 3) PARAMETER Input Low Voltage (Note 11) SYMBOL VIL CONDITIONS (All inputs except M/Z) MIN TYP MAX UNITS 2.2V < VDDIO < 5.5V 0.3 x VDDIO V 1.8V < VDDIO < 2.2V 0.2 x VDDIO 0.3 x VDD 2.7V < VDD < 5.
PAGE 7
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface ELECTRICAL CHARACTERISTICS (continued) (VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SDA and SCL Receiving Fall Time tF 20 + CB/10 300 ns SDA Transmitting Fall Time tF 20 + CB/10 250 ns tSU;STO 0.
PAGE 8
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface Typical Operating Characteristics (MAX5825, 12-bit performance, TA = +25°C, unless otherwise noted.) INL vs. CODE VDD = VREF = 5V NO LOAD 0.8 0.6 0.2 0 -0.2 0 -0.2 -0.4 -0.4 -0.4 -0.6 -0.6 -0.6 -0.8 -0.8 -0.8 -1.0 -1.0 512 1024 1536 2048 2560 3072 3584 4096 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 DNL vs. CODE VDD = VREF 0.8 0.6 0.4 MAX INL 0.2 0 -0.
PAGE 9
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface Typical Operating Characteristics (continued) (MAX5825, 12-bit performance, TA = +25°C, unless otherwise noted.) GAIN ERROR (VDD = 3V) -0.05 VREF (INTERNAL) = 2.5V, VDD = 5V 1.2 -0.10 0.8 TA = +85°C TA = +25°C TA = -40°C 0.4 3.1 3.5 3.9 4.3 0.6 0.2 0 2.7 3.1 VDD = VREF = 5V VDD = 5V, VREF = 2.5V VDD = 5V, VREF = 2.048V 0.8 4.7 5.1 5.5 3.5 3.9 4.3 4.7 5.
PAGE 10
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface Typical Operating Characteristics (continued) (MAX5825, 12-bit performance, TA = +25°C, unless otherwise noted.) MAJOR CODE TRANSITION GLITCH ENERGY (VDD = VREF = 5V, RL = 2kI, CL = 200pF) MAJOR CODE TRANSITION GLITCH ENERGY (VDD = VREF = 5V, RL = 2kI, CL = 200pF) MAX5823 toc19 MAX5823 toc18 VOUT 3.
PAGE 11
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface Typical Operating Characteristics (continued) (MAX5825, 12-bit performance, TA = +25°C, unless otherwise noted.) CHANNEL-TO-CHANNEL FEEDTHROUGH (VDD = VREF = 5V, TA = +25NC, RL = 2kI, CL = 200pF) CHANNEL-TO-CHANNEL FEEDTHROUGH (VDD = 5V, VREF = 4.
PAGE 12
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface Typical Operating Characteristics (continued) (MAX5825, 12-bit performance, TA = +25°C, unless otherwise noted.) 0.1Hz TO 10Hz OUTPUT NOISE, EXTERNAL REFERENCE (VDD = 5V, VREF = 4.5V) 0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL REFERENCE (VDD = 5V, VREF = 2.
PAGE 13
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface Typical Operating Characteristics (continued) (MAX5825, 12-bit performance, TA = +25°C, unless otherwise noted.) WATCHDOG TIMER FREQUENCY vs.
PAGE 14
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface Pin Configurations TOP VIEW TOP VIEW REF 1 MAX5823/MAX5824/MAX5825 + 20 M/Z OUT0 2 19 GND OUT1 3 18 LDAC OUT2 4 17 CLR OUT3 5 OUT4 6 MAX5823 MAX5824 MAX5825 16 IRQ 15 SDA OUT5 7 14 SCL OUT6 8 13 ADDR0 OUT7 9 12 ADDR1 VDD 10 11 VDDIO 1 2 3 4 5 + OUT6 OUT7 VDDIO ADDR1 ADDR0 OUT5 OUT4 VDD SDA SCL OUT2 OUT3 M/Z CLR IRQ OU
PAGE 15
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface Detailed Description The MAX5823/MAX5824/MAX5825 are 8-channel, lowpower, 8-/10-/12-bit buffered voltage-output DACs. The 2.7V to 5.5V wide supply voltage range and low-power consumption accommodates most low-power and lowvoltage applications. The devices present a 100kI load to the external reference. The internal output buffers allow rail-to-rail operation.
PAGE 16
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface External Reference The external reference input has a typical input impedance of 100kI and accepts an input voltage from +1.24V to VDD. Apply an external voltage between REF and GND to use an external reference. The MAX5823/MAX5824/MAX5825 power up and reset to external reference mode. Visit www.maximintegrated.
PAGE 17
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface Interface Power Supply (VDDIO) The MAX5823/MAX5824/MAX5825 feature a separate supply input (VDDIO) for the digital interface (1.8V to 5.5V). Connect VDDIO to the I/O supply of the host processor. I2C Serial Interface The MAX5823/MAX5824/MAX5825 feature an I2C-/ SMBusK-compatible, 2-wire serial interface consisting of a serial data line (SDA) and a serial clock line (SCL).
PAGE 18
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface I2C Slave Address The slave address is defined as the seven most significant bits (MSBs) followed by the R/W bit. See Figure 4. The three most significant bits are 001 with the 4 LSBs determined by ADDR1 and ADDR0 as shown in Table 1. Setting the R/W bit to 1 configures the MAX5823/ MAX5824/MAX5825 for read mode.
PAGE 19
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface I2C Write Operations Combined Format I2C Readback Operations A master device communicates with the MAX5823/ MAX5824/MAX5825 by transmitting the proper slave address followed by command and data words. Each transmit sequence is framed by a START or Repeated START condition and a STOP condition as described above.
PAGE 20
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface Readback of individual RETURN registers is supported for RETURN commands (B[23:20] = 0111). For this command, which supports a DAC address, the requested channel RETURN register content will be returned, along with the selected DAC address. If all DACs are selected, readback will begin with RETURN0 content and will progress through the remaining DAC channels.
PAGE 21
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface Table 3.
PAGE 22
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface presented for readback, followed by a STOP condition. If additional bytes beyond those required to readback the requested data are provided, the MAX5823/MAX5824/ MAX5825 will continue to readback ones. µC SDA SCL MAX5823 MAX5824 MAX5825 SCL SDA ADDR0 ADDR1 MAX5823 MAX5824 MAX5825 +5V SCL SDA ADDR0 ADDR1 Figure 8.
PAGE 23
0 0 0 0 0 0 0 0 0 0 WDOG REF SW_GATE_CLR SW_GATE_SET WD_REFRESH WD_RESET SW_CLEAR SW_RESET POWER CONFIG 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 0 REF Pow- REF Mode 00 = EXT er 0 = 01 = 2.5V DAC 10 = 2.0V 1= 11 = 4.
PAGE 24
Maxim Integrated 1 1 1 1 1 1 1 1 CODEn LOADn CODEn_ LOAD_ALL CODEn_LOADn CODE_ALL LOAD_ALL CODE_ALL LOAD_ALL RETURN_ALL 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 X X X 1 1 0 0 X X X 1 0 1 0 DAC SELECTION DAC SELECTION DAC SELECTION DAC SELECTION DAC SELECTION 0 DAC 7 X X X X X DAC 6 X X X X X X X X X X X X X X X X X X X
PAGE 25
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface RETURNn Command The RETURNn command (B[23:20] = 0111) sets the programmable default RETURN value. This value is used for all future watchdog, clear, and gate operations when RET is selected for the DAC using the DEFAULT command. Issuing this command with DAC_ADDRESS set to all DACs will program the value for all RETURN registers and is equivalent to RETURN_ALL.
PAGE 26
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface WDOG Command The WDOG command (B[23:20] = 0001) updates the watchdog timeout settings and safety levels for the device. Timeout thresholds are selected in 1ms increments (1ms to 4095ms are available). The WD_MASK bit can be used to mask the IRQ operation in response to the watchdog status, if WD_MASK = 1, watchdog alarms will not assert IRQ.
PAGE 27
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface REF Command The REF command (B[23:20] = 0010) updates the global reference setting used for all DAC channels. If an internal reference mode is selected, bit RF2 (B18) defines the reference power mode. If RF2 is set to zero (default), the reference will be powered down any time all DAC channels are powered down (i.e. the device is in STANDBY mode).
PAGE 28
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface POWER Command The POWER command (B[23:20] = 0100) updates the power mode settings of the selected DACs. DACs that are not selected do not update their power settings in response to the command. The new power setting is determined by bits PD[1:0] (B[7:6]) while the affected DAC(s) are selected using B[15:8]).
PAGE 29
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface LDB = 1: DAC latch is transparent, the CODE register content controls the DAC output directly.
PAGE 30
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface DEFAULT Command The DEFAULT command (B[23:20] = 0110) selects the default value for selected DACs. DACs which are not selected do not update their default settings in response to the command. These default values are used for all future watchdog, clear, and gate operations.
PAGE 31
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface Applications Information Power-On Reset (POR) Power Supplies and Bypassing Considerations Gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step.
PAGE 32
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface Detailed Functional Diagram VDD REF RIN 100kI INTERNAL/EXTERNAL REFERENCE (USER OPTION) CODE REGISTER 0 DAC LATCH 0 8-/10-/12-BIT DAC0 OUT0 BUFFER 0 VDDIO CODE CLEAR / RESET GATE/ CLEAR / RESET LOAD CHANNEL 0 DAC CONTROL LOGIC CONTROL LOGIC SCL 100kI 1kI POWER-DOWN DAC CHANNEL 0 DAC CHANNEL 1 OUT1 DAC CHANNEL 2 OUT2 DAC CHANNEL 3 OUT3 DAC CHANNEL 4 OUT4 DAC
PAGE 33
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface Typical Operating Circuits 100nF RPU = 5kI RPU = 5kI 100nF 4.7µF RPU = 5kI VDDIO VDD LDAC SDA OUT DAC SCL ADDR0 µC ADDR1 MAX5823 MAX5824 MAX5825 R1 REF R2 CLR R1 = R2 IRQ M/Z GND NOTE: BIPOLAR OPERATING CIRCUIT, ONE CHANNEL SHOWN 100nF RPU = 5kI RPU = 5kI 4.
PAGE 34
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface Ordering Information PART TEMP RANGE PIN-PACKAGE RESOLUTION (BIT) MAX5823AUP+ -40°C to +125°C 20 TSSOP 8 MAX5824AUP+ -40°C to +125°C 20 TSSOP 10 MAX5825AAUP+ -40°C to +125°C 20 TSSOP 12 MAX5825AWP+T -40°C to +125°C 20 WLP 12 MAX5825BAUP+ -40°C to +125°C 20 TSSOP Note: All devices are specified over the -40°C to +125°C temperature range.
PAGE 35
MAX5823/MAX5824/MAX5825 Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface Revision History REVISION NUMBER REVISION DATE 0 2/12 Initial release 1 11/12 Revised the Electrical Characteristics, Ordering Information, Typical Operating Characteristics, Pin Configuration, Pin Description, CODEn_LOADn Command, and Offset Error sections. Added the Zero-Scale Error and Full-Scale Error sections. 2 2/13 Released the MAX5823/MAX5824/MAX5825B.