Datasheet

6Maxim Integrated
MAX5713/MAX5714/MAX5715
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 5.5V, V
DDIO
= 1.8V to 5.5V, V
GND
= 0V, C
L
= 200pF, R
L
= 2kI, T
A
= -40NC to +125NC, unless otherwise noted. Typical
values are at T
A
= +25NC.) (Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Low Voltage (Note 11) V
IL
2.2V < V
DDIO
< 5.5V
0.3 x
V
DDIO
V
1.8V < V
DDIO
< 2.2V
0.2 x
V
DDIO
Input Leakage Current I
IN
V
IN
= 0V or V
DDIO
(Note 11) Q0.1 Q1 FA
Input Capacitance (Note 10) C
IN
3 pF
DIGITAL OUTPUT (RDY)
Output High Voltage V
OH
V
DDIO
> 2.5V, I
SOURCE
= 3mA
V
DDIO
- 0.2
V
V
DDIO
> 1.8V, I
SOURCE
= 2mA
V
DDIO
- 0.2
V
Output Low Voltage V
OL
V
DDIO
> 2.5V, I
SINK
= 3mA 0.2 V
V
DDIO
> 1.8V, I
SINK
= 2mA 0.2 V
Output Short-Circuit Current I
OSS
I
SINK
, I
SOURCE
±100 mA
SPI TIMING CHARACTERISTICS (CSB, SCLK, DIN, RDY)
SCLK Frequency
f
SCLK
2.7V < V
DDIO
< 5.5V, standalone,
daisy chain (Note 12)
0 50
MHz
0 20
1.8V < V
DDIO
< 2.7V, standalone,
daisy chain (Note 12)
0 33
0 20
SCLK Period
t
SCLK
2.7V < V
DDIO
< 5.5V 20
ns
1.8V < V
DDIO
< 2.7V 30
SCLK Pulse Width High
t
CH
8 ns
SCLK Pulse Width Low
t
CL
8 ns
CSB Fall to SCLK Fall Setup Time
t
CSS0
To first SCLK falling edge 8 ns
CSB Fall to SCLK Fall Hold Time
t
CSH0
Applies to inactive SCLK falling edge
preceding the first SCLK falling edge
0 ns
CSB Rise to SCLK Fall Hold Time
t
CSH1
Applies to the 24th SCLK falling edge 0 ns
CSB Rise to SCLK Fall
t
CSA
Applies to the 24th SCLK falling edge,
aborted sequence
12 ns
SCLK Fall to CSB Fall
t
CSF
Applies to 24th SCLK falling edge 100 ns
CSB Pulse Width High
t
CSPW
20 ns
DIN to SCLK Fall Setup Time
t
DS
5 ns
DIN to SCLK Fall Hold Time
t
DH
4.5 ns
CLR Pulse Width Low
t
CLPW
20 ns
CLR Rise to CSB Fall
t
CSC
Required for command to be executed 20 ns
LDAC Pulse Width Low
t
LDPW
20 ns
LDAC Fall to SCLK Fall Hold
t
LDH
Applies to 24th SCLK falling edge, 20 ns