Datasheet

MAX5712
12-Bit, Low-Power, Rail-to-Rail
Voltage-Output Serial DAC in SOT23
3
Maxim Integrated
Note 1: DC Specifications are tested without output loads.
Note 2: Linearity guaranteed from code 115 to code 3981.
Note 3: Offset and gain error limit the FSR.
Note 4: Guaranteed by design.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX
UNITS
POWER REQUIREMENTS
Supply Voltage Range V
DD
2.7 5.5 V
All digital inputs at 0 or V
DD
, V
DD
= +3.6V 85 150
Supply Current with No-Load I
DD
All digital inputs at 0 or V
DD
, V
DD
= +5.5V 105 187
µA
Power-Down Supply Current I
DDPD
All digital inputs at 0 or V
DD
, V
DD
= +5.5V
0.29 1
µA
TIMING CHARACTERISTICS (FIGURE 1) (TIMING IS TESTED WITH NO-LOAD)
SCLK Clock Frequency f
SCLK
0 20 MHz
SCLK Pulse Width High t
CH
20 ns
SCLK Pulse Width Low t
CL
20 ns
CS Fall-to-SLCK Rise Setup
t
CSS
15 ns
DIN Setup Time t
DS
15 ns
DIN Hold Time t
DH
0ns
SCLK Falling Edge-to-CS
Rising Edge
t
CSH
10 ns
CS Pulse Width High t
CSW
80 ns
Typical Operating Characteristics
(T
A
= +25°C, unless otherwise noted.)
-16
-4
-8
-12
0
4
12
8
16
0 512 1024 1536 2048 2560 3072 3584 4096
INTEGRAL NONLINEARITY
vs. CODE, T
A
= +25°C
MAX5712 toc01
CODE
INL (LSB)
V
DD
= +5V
V
DD
= +3V
-0.2
-0.4
-0.6
-0.8
-1.0
0.2
0.0
0.4
0.8
0.6
1.0
0 512 1024 1536 2048 2560 3072 3584 4096
DIFFERENTIAL NONLINEARITY
vs. CODE, T
A
= +25°C
MAX5712 toc02
CODE
DNL (LSB)
-0.2
-0.4
-0.6
-0.8
-1.0
0.2
0.0
0.4
0.8
0.6
1.0
0 512 1024 1536 2048 2560 3072 3584 4096
TOTAL UNADJUSTED ERROR
vs. CODE, T
A
= +25°C
MAX5712 toc03
CODE
TUE (%)
V
DD
= +5V
V
DD
= +3V
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +2.7V to +5.5V, GND = 0, R
L
= 5kΩ, C
L
= 200pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V
DD
= +5V.
T
A
= +25°C)