Datasheet

The inputs of unused drivers may be left unconnected
because they have internal 400kΩ pull-ups to V
CC
.
Unused inputs may also be connected to GND or V
CC
,
but V
CC
provides lower power consumption because of
the internal pull-ups.
EIA/TIA-562 and EIA/TIA-232 Receivers
The MAX563’s receivers convert ±3.7V to ±13.2V
EIA/TIA-562 signal levels into +3V logic levels; they are
rated to receive signals up to ±25V to accommodate
EIA/TIA-232 signals as well. Both receivers invert. Their
inputs are each equipped with an internal 5kΩ (nomi-
nal) terminating resistor connected to ground, and the
input logic thresholds are 0.4V and 2.4V. The positive
logic-low threshold (V
IL
) ensures the receiver outputs
remain high whenever their inputs are left open.
The receivers are active when EN is low, and have
high-impedance outputs when EN is high.
When SHDN is high, the receivers have hysteresis.
This produces clean output transitions, even with slow-
moving input signals that exhibit moderate amounts of
noise and ringing. When shut down, the receivers have
no hysteresis, and the propagation delay increases.
Shutdown and Enable Control
The SHDN and EN controls are independent. Both
receivers are always active when EN is low. With EN
low and SHDN high, the receivers operate at full speed
and have hysteresis. When active in shutdown mode
(EN = SHDN = low), the receivers operate at reduced
power and speed, and without hysteresis.
The charge pumps and transmitters operate only when
SHDN is high; they are unaffected by EN. When shut
down (SHDN = low) or unpowered (V
CC
= 0V), the
transmitter outputs are high impedance if they are
backdriven with voltages not exceeding ±15V. The pull-
up resistors at the driver inputs are disconnected in
shutdown mode to save power. During shutdown, V+ is
pulled down to V
CC
, and V- rises to GND.
_______________________________________________________________________________________ 5
MAX563
+3.3V-Powered, EIA/TIA-562 Dual Transceiver
with Receivers Active in Shutdown
V+
GND
MAX563
0.1µF
V
CC
0.1µF
R1 & R2
T1 & T2
0.1µF
C1+
C1-
C2+
C2-
V
CC
+3.6V
T
OUT
R
OUT
400k
5k
I
SHDN
0V +3.6V
DRIVE
0.1µF
0.1µF
3k
+3.6V
R
IN
T
IN
EN 
SHDN
V-
+3.6V
V+
OV
V-
t
PHLT
OV
INPUT
OUTPUT
t
PLHT
+3V
INPUT
OUTPUT
50%
50%
+3V
50%
50%
V
CC
GND
t
PLHR
t
PLHS
t
PHLR
t
PHLS
0V
Figure 1. Shutdown Current Test Circuit
Figure 2. Transmitter Propagation Delay Timing
Figure 3. Receiver Propagation Delay Timing