Datasheet
MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
9
Maxim Integrated
Detailed Description
Digital-to-Analog Converter
The MAX5631/MAX5632/MAX5633 16-bit digital-to-ana-
log converters (DAC) are composed of two matched
sections. The four MSBs are derived through 15 identi-
cal matched resistors and the lower 12 bits are derived
through a 12-bit inverted R-2R ladder.
Sample-and-Hold Amplifiers
The MAX5631/MAX5632/MAX5633 contain 32 buffered
sample/hold circuits with internal hold capacitors.
Internal hold capacitors minimize leakage current,
dielectric absorption, feedthrough, and required board
space. MAX5631/MAX5632/MAX5633 provide a very low
1mV/s droop rate.
Output
The MAX5631/MAX5632/MAX5633 include output buffers
on each channel. The device contains output resistors in
series with the buffer output (Figure 3) for ease of output
filtering and capacitive load driving stability.
Output loads increase the analog supply current (I
DD
and I
SS
). Excessively loading the outputs drastically
increases power dissipation. Do not exceed the maxi-
mum power dissipation specified in the
Absolute
Maximum Ratings
.
The maximum output voltage range depends on the
analog supply voltages available and the output clamp
voltages (see
Output Clamp
).
The device has a fixed theoretical output range deter-
mined by the reference voltage, gain, and midscale offset.
The output voltage for a given input code is calculated
with the following:
where code is the decimal value of the DAC input
code, V
REF
is the reference voltage, and V
GS
is the
V
code
V
V
OUT REF
GS
=
⎛
⎝
⎜
⎞
⎠
⎟
××
×
()
+
65535
5 2428 .-
1.6214 V
REF
VVVVV
SS OUT DD
+
()
≤≤
()
075 24..
_
-
Table 1. Code Table
DAC INPUT CODE
MSB LSB
NOMINAL OUTPUT
VOLTAGE (V)
V
REF
= +2.5V
1111 1111 1111 1111 9.0535 Full-scale output
1100 0111 0100 1010 6.15 Maximum output with V
DD
= 8.55V
1000 0000 0000 0000 2.5 Midscale output
0100 1111 0010 1100 0
V
OUT_
= 0. All outputs default to this code after power-up
0010 1000 0001 1100 -2.0 Minimum output with V
SS
= -2.75V
0000 0000 0000 0000 -4.0535 Zero-scale output
t
CSHO
t
CH
t
CSSO
t
CL
t
DH
t
DS
t
CSH1
t
CSS1
CS
SCLK
DIN
B23 B22
B0
Figure 2. Serial Interface Timing Diagram