Datasheet

MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
3
Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +10V, V
SS
= -4V, V
LOGIC
= V
LDAC
= V
LSHA
= +5V, V
REF
= +2.5V, V
AGND
= V
DGND
= V
GS
= 0V, R
L
≥ 10MΩ, C
L
= 50pF,
CLKSEL = +5V, f
ECLK
= 400kHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS
Sample-and-Hold Settling (Note 4)
0.08
%
SCLK Feedthrough 0.5
nV-s
f
SEQ
Feedthrough 0.5
nV-s
Hold-Step
0.25
1mV
Droop Rate V
OUT_
= 0V (Note 5), T
A
= +25°C 1 40
mV/s
Output Noise
250
µV
RMS
REFERENCE INPUT
Input Resistance 7kΩ
Reference Input Voltage V
REF
2.5 V
GROUND-SENSE INPUT
Input Voltage Range V
GS
-0.5
0.5 V
Input Bias Current I
GS
-0.5V ≤ V
GS
≤ 0.5V -60 0 µA
GS Gain (Note 6)
0.998
1
1.002
V/V
DIGITAL INTERFACE DC CHARACTERISTICS
Input High Voltage V
IH
2.0 V
Input Low Voltage V
IL
0.8 V
Input Current ±1µA
TIMING CHARACTERISTICS (FIGURE 2)
Sequencer Clock Frequency f
SEQ
Internal oscillator 80
100 120
kHz
External Clock Frequency f
ECLK
(Note 7)
480
kHz
SCLK Frequency f
SCLK
20
MHz
SCLK Pulse Width High t
CH
15 ns
SCLK Pulse Width Low t
CL
15 ns
CS Low to SCLK High Setup
Time
t
CSSO
15 ns
CS High to SCLK High Setup
Time
t
CSS1
15 ns
SCLK High to CS Low Hold Time
t
CSH0
10 ns