Datasheet

MAX5631/MAX5632/MAX5633
16-Bit DACs with 32-Channel
Sample-and-Hold Outputs
11
Maxim Integrated
rising edge of SCLK after CS goes low will clock in the
MSB of the input word.
When each serial word is complete, the value is stored
in the SRAM at the address indicated and the control
bits are saved. Note that data may be corrupted if CS is
not held low for an integer multiple of 24 bits.
All of the digital inputs include Schmitt-trigger buffers to
accept slow-transition interfaces. Their switching
threshold is compatible with TTL and most CMOS logic
levels.
Serial Input Data Format and
Control Codes
The 24-bit serial input format, shown in Figure 4, compris-
es of 16 data bits (D15–D0), five address bits (A4–A0),
two control bits (C1, C0), and a fill zero. The address
code selects the output channel as shown in Table 2. The
control code configures the device as follows:
1) If C1 = 1, Immediate Update Mode is selected.
If C1 = 0, Burst Mode is selected.
2) If C0 = 0, the internal sequencer clock is selected. If
C0 = 1, the external sequencer clock is selected.
This must be repeated with each data word to main-
tain external input.
A4 A3 A2 A1 A0 OUTPUT
00000OUT0 selected
00001OUT1 selected
00010OUT2 selected
00011OUT3 selected
00100OUT4 selected
00101OUT5 selected
00110OUT6 selected
00111OUT7 selected
01000OUT8 selected
01001OUT9 selected
01010OUT10 selected
01011OUT11 selected
01100OUT12 selected
01101OUT13 selected
01110OUT14 selected
01111OUT15 selected
10000OUT16 selected
10001OUT17 selected
10010OUT18 selected
10011OUT19 selected
10100OUT20 selected
10101OUT21 selected
10110OUT22 selected
10111OUT23 selected
11000OUT24 selected
11001OUT25 selected
11010OUT26 selected
11011OUT27 selected
11100OUT28 selected
11101OUT29 selected
11110OUT30 selected
11111OUT31 selected
Table 2. Channel/Output Selection