Datasheet

MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
6 _______________________________________________________________________________________
TIMING CHARACTERISTICS—DSP Mode Disabled (3V, 3.3V, 5V Logic) (Figure 1)
(DV
DD
= 2.7V to 5.25V, V
AGND
= 0V, V
DGND
= 0V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Frequency f
SCLK
2.7V < DV
DD
< 5.25V 20 MHz
SCLK Pulse-Width High t
CH
(Note 7) 20 ns
SCLK Pulse-Width Low t
CL
(Note 7) 20 ns
CS Fall to SCLK Rise Setup Time t
CSS
10 ns
SCLK Rise to CS Rise Hold Time t
CSH
5ns
SCLK Rise to CS Fall Setup t
CS0
10 ns
DIN to SCLK Rise Setup Time t
DS
12 ns
DIN to SCLK Rise Hold Time t
DH
5ns
SCLK Rise to DOUTDC1 Valid
Propagation Delay
t
DO1
C
L
= 20pF, UPIO_ = DOUTDC1 mode 30 ns
SCLK Fall to DOUT_ Valid
Propagation Delay
t
DO2
C
L
= 20pF, UPIO_ = DOUTDC0 or DOUTRB
mode
30 ns
CS Rise to SCLK Rise Hold Time t
CS1
MICROWIRE and SPI modes 0 and 3 10 ns
CS Pulse-Width High t
CSW
45 ns
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when Exiting
DOUTDC0, DOUTDC1, and UPIO
Modes
t
DOZ
C
L
= 20pF, from end of write cycle to UPIO_
in high impedance
100 ns
DOUTRB Tri-State Time from CS
Rise
t
DRBZ
C
L
= 20pF, from rising edge of CS to UPIO_
in high impedance
20 ns
DOUTRB Tri-State Enable Time
from 8th SCLK Rise
t
ZEN
C
L
= 20pF, from 8th rising edge of SCLK to
UPIO_ driven out of tri-state
0ns
LDAC Pulse-Width Low t
LDL
Figure 5 20 ns
LDAC Effective Delay t
LDS
Figure 6 100 ns
CLR, MID, SET Pulse-Width Low t
CMS
Figure 5 20 ns
GPO Output Settling Time t
GP
Figure 6 100 ns
GPO Output High-Impedance
Time
t
GPZ
100 ns