Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - DA converter (DAC) TSSOP 24

MAX5590–MAX5595

Buffered, Fast-Settling, Octal, 12/10/8-Bit,

Voltage-Output DACs

______________________________________________________________________________________ 27

UPIO Configuration

Table 22 lists the possible configurations for UPIO1 and

UPIO2. UPIO1 and UPIO2 use the selected function

when configured by the UP3–UP0 configuration bits.

LDAC

LDAC controls the loading of the DAC registers. When

LDAC is high, the DAC registers are latched, and any

change in the input registers does not affect the con-

tents of the DAC registers or the DAC outputs. When

LDAC is low, the DAC registers are transparent, and the

values stored in the input registers are fed directly to the

DAC registers, and the DAC outputs are updated.

Drive LDAC low to asynchronously load the DAC regis-

ters from their corresponding input registers (DACs that

are in shutdown remain shut down). The LDAC input

does not require any activity on CS, SCLK, or DIN to

take effect. If LDAC is brought low coincident with a ris-

ing edge of CS (which executes a serial command

modifying the value of either DAC input register), then

LDAC must remain asserted for at least 120ns following

the CS rising edge. This requirement applies only for

serial commands that modify the value of the DAC input

registers. See Figures 5 and 6 for timing details.

Table 22. UPIO Configuration Register Bits (UP3–UP0)

UPIO CONFIGURATION BITS

UP3 UP2 UP1 UP0

FUNCTION DESCRIPTION

0000 LDAC

Active-Low Load DAC Input. Drive low to asynchronously load all DAC registers

with data from input registers.

0001 SET Active-Low Input. Drive low to set all input and DAC registers to full scale.

0010 MID Active-Low Input. Drive low to set all input and DAC registers to midscale.

0011 CLR Active-Low Input. Drive low to set all input and DAC registers to zero scale.

0100 PDL Active-Low Power-Down Lockout Input. Drive low to disable software shutdown.

0101Reserved This mode is reserved. Do not use.

0110SHDN1K

Active-Low 1kΩ Shutdown Input. Overrides PD_1 and PD_0 settings. For the

MAX5590/MAX5592/MAX5594, drive SHDN1K low to pull OUTA–OUTH to AGND

with 1kΩ. For the MAX5591/MAX5593/MAX5595, drive SHDN1K low to leave

OUTA–OUTH high impedance.

0111SHDN100K

Active-Low 100kΩ Shutdown Input. Overrides PD_1 and PD_0 settings. For the

MAX5590/MAX5592/MAX5594, drive SHDN100K low to pull OUTA–OUTH to

AGND with 100kΩ. For the MAX5591/MAX5593/MAX5595, drive low to leave

OUTA–OUTH high impedance.

1000DOUTRB Data Read-Back Output

1001DOUTDC0

Mode 0 Daisy-Chain Data Output. Data is clocked out on the falling edge of

1010DOUTDC1 Mode 1 Daisy-Chain Data Output. Data is clocked out on the rising edge of SCLK.

1011 GPIGeneral-Purpose Logic Input

1100 GPOLGeneral-Purpose Logic-Low Output

1101GPOH General-Purpose Logic-High Output

1110TOGG

Toggle Input. Toggles DAC outputs between data in input registers and data in

DAC registers. Drive low to set all DAC outputs to values stored in input registers.

Drive high to set all DAC outputs to values stored in DAC registers.

1111 FAST

Fast/Slow Settling-Time-Mode Input. Drive low to select FAST (3µs) mode or drive

high to select SLOW (6µs) settling mode. Overrides the SPDA–SPDH settings.