Datasheet

MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
22 ______________________________________________________________________________________
CONTROL BITS DATA BITS
DATA
C3 C2 C1 C0 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
FUNCTION
READ INPUT AND DAC REGISTERS A–H
DIN 1101000X 1 1 1 1 11111111 1111XXXXXXXX
DOUTRB X X X X X X X X
DDA_11
DDA_10
DDA_9
DDA_8
DDA_7
DDA_6
DDA_5
DDA_4
DDA_3
DDA_2
DDA_1
DDA_0
IDA_11
IDA_10
IDA_9
IDA_8
IDA_7
IDA_6
IDA_5
IDA_4
IDA_3
IDA_2
IDA_1
IDA_0
Read input register A and DAC register A (all 24 bits).**
†
DIN 1101001X 1 1 1 1 11111111 1111XXXXXXXX
DOUTRB X X X X X X X X
DDB_11
DDB_10
DDB_9
DDB_8
DDB_7
DDB_6
DDB_5
DDB_4
DDB_3
DDB_2
DDB_1
DDB_0
IDB_11
IDB_10
IDB_9
IDB_8
IDB_7
IDB_6
IDB_5
IDB_4
IDB_3
IDB_2
IDB_1
IDB_0
Read input register B and DAC register B (all 24 bits).**
†
DIN 1101010X 1 1 1 1 11111111 1111XXXXXXXX
DOUTRB X X X X X X X X
DDC_11
DDC_10
DDC_9
DDC_8
DDC_7
DDC_6
DDC_5
DDC_4
DDC_3
DDC_2
DDC_1
DDC_0
IDC_11
IDC_10
IDC_9
IDC_8
IDC_7
IDC_6
IDC_5
IDC_4
IDC_3
IDC_2
IDC_1
IDC_0
Read input register C and DAC register C (all 24 bits).**
†
DIN 1101011X 1 1 1 1 11111111 1111XXXXXXXX
DOUTRB X X X X X X X X
DDD_11
DDD_10
DDD_9
DDD_8
DDD_7
DDD_6
DDD_5
DDD_4
DDD_3
DDD_2
DDD_1
DDD_0
IDD_11
IDD_10
IDD_9
IDD_8
IDD_7
IDD_6
IDD_5
IDD_4
IDD_3
IDD_2
IDD_1
IDD_0
Read input register D and DAC register D (all 24 bits).**
†
DIN 1101100X 1 1 1 1 11111111 1111XXXXXXXX
DOUTRB X X X X X X X X
DDE_11
DDE_10
DDE_9
DDE_8
DDE_7
DDE_6
DDE_5
DDE_4
DDE_3
DDE_2
DDE_1
DDE_0
IDE_11
IDE_10
IDE_9
IDE_8
IDE_7
IDE_6
IDE_5
IDE_4
IDE_3
IDE_2
IDE_1
IDE_0
Read input register E and DAC register E (all 24 bits).**
†
DIN 1101101X 1 1 1 1 11111111 1111XXXXXXXX
DOUTRB X X X X X X X X
DDF_11
DDF_10
DDF_9
DDF_8
DDF_7
DDF_6
DDF_5
DDF_4
DDF_3
DDF_2
DDF_1
DDF_0
IDF_11
IDF_10
IDF_9
IDF_8
IDF_7
IDF_6
IDF_5
IDF_4
IDF_3
IDF_2
IDF_1
IDF_0
Read input register F and DAC register F (all 24 bits).**
†
DIN 1101110X 1 1 1 1 11111111 1111XXXXXXXX
DOUTRB X X X X X X X X
DDG_11
DDG_10
DDG_9
DDG_8
DDG_7
DDG_6
DDG_5
DDG_4
DDG_3
DDG_2
DDG_1
DDG_0
IDG_11
IDG_10
IDG_9
IDG_8
IDG_7
IDG_6
IDG_5
IDG_4
IDG_3
IDG_2
IDG_1
IDG_0
Read input register G and DAC register G (all 24 bits).**
†
DIN 1101111X 1 1 1 1 11111111 1111XXXXXXXX
DOUTRB X X X X X X X X
DDH_11
DDH_10
DDH_9
DDH_8
DDH_7
DDH_6
DDH_5
DDH_4
DDH_3
DDH_2
DDH_1
DDH_0
IDH_11
IDH_10
IDH_9
IDH_8
IDH_7
IDH_6
IDH_5
IDH_4
IDH_3
IDH_2
IDH_1
IDH_0
Read input register H and DAC register H (all 24 bits).**
†
Table 2c. 24-Bit Read Commands
X = Don’t care. **
D23–D12 represent the 12-bit data from the corresponding DAC register. D11–D0 represent the 12-bit data from the corresponding input register. For
the MAX5592/MAX5593, bits D13, D12, D1, and D0 are zero bits. For the MAX5594/MAX5595, bits D15–D12 and D3–D0 are zero bits.
†
During readback, all ones (code FF) must be clocked into DIN for all 24 bits. No command can be issued before all 24 bits have been clocked out.
CS must be kept low while all 24 bits are being clocked out.