Datasheet
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
20 ______________________________________________________________________________________
CONTROL BITS DATA BITS
DATA
C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
FUNCTION
SELECT BITS
DIN 1000XXXXMHMGMFMEMDMCMBMA
Load D AC r eg i ster “_”
fr om i np ut r eg i ster “_”
w hen M _ = 1. D AC r eg i ster
“_” i s unchang ed i f M _ = 0.
LOADING INPUT AND DAC REGISTERS (A–H)
DIN 1001D11D10D9D8D7D6D5D4D3/0 D2/0 D1/0 D0/0
Load all input registers
A–H from shift register;
DAC registers are
unchanged. DAC outputs
are unchanged.*
DIN 1010D11D10D9D8D7D6D5D4D3/0 D2/0 D1/0 D0/0
Load all input and DAC
registers A–H from shift
register. DAC outputs
updated.
SHUTDOWN BITS
DIN 10110000PDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0
Write DACA–DACD
shutdown-mode bits.
See Table 8.
DIN 10110001XXXXXXXX
DOUTRB XXXXXXXXPDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0
Read-back DACA–DACD
shutdown-mode bits.
DIN 10110010PDH1 PDH0 PDG1 PDG0 PDF1 PDF0 PDE1 PDE0
Write DACE–DACH
shutdown-mode bits.
See Table 8.
DIN 10110011XXXXXXXX
DOUTRB XXXXXXXXPDH1 PDH0 PDG1 PDG0 PDF1 PDF0 PDE1 PDE0
Read-back DACE–DACH
shutdown-mode bits.
DIN 10110100PDCHPDCG PDCF PDCE PDCD PDCC PDCB PDCA
Write DAC shutdown-
control bits.
DIN 10110101XXXXXXXX
DOUTRB XXXXXXXXPDCHPDCG PDCF PDCE PDCD PDCC PDCB PDCA
Read-back DAC
shutdown-control settings.
Table 2b. Advanced-Feature Programming Commands
X = Don’t care.
*
For the MAX5592/MAX5593 (10-bit version), D11–D2 are the significant bits and D1 and D0 are sub-bits. For the MAX5594/MAX5595 (8-bit version),
D11–D4 are the significant bits and D3–D0 are sub-bits. Set all sub-bits to zero during the write commands.