Datasheet

MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
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Pin Description
PIN
MAX5590
MAX5592
MAX5594
MAX5591
MAX5593
MAX5595
NAME FUNCTION
11AV
DD
Analog Supply
2 2 AGND Analog Ground
3 3 OUTA DACA Output
4, 8, 17, 21 — N.C. No Connection. Not internally connected.
5 6 OUTB DACB Output
6 7 OUTC DACC Output
7 10 OUTD DACD Output
911CS Active-Low Chip-Select Input
10 12 SCLK Serial Clock Input
11 13 DIN Serial Data Input
12 14 DSP
Clock Enable. Connect DSP to DV
DD
at power-up to transfer data on the rising edge
of SCLK. Connect DSP to GND to transfer data on the falling edge of SCLK.
Connect DSP to DGND at power-up to transfer data on the falling edge of SCLK.
13 15 DV
DD
Digital Supply
14 16 DGND Digital Ground
15 17 UPIO1 User-Programmable Input/Output 1
16 18 UPIO2 User-Programmable Input/Output 2
18 19 OUTE DACE Output
19 22 OUTF DACF Output
20 23 OUTG DACG Output
22 26 OUTH DACH Output
23 27 PU
Power-Up State Select Input. Connect PU to DV
DD
to set OUTA–OUTH to full scale
upon power-up. Connect PU to DGND to set OUTA–OUTH to zero upon power-up.
Leave PU unconnected at power-up to set OUTA–OUTH to midscale.
24 28 REF Reference Input
— 4 FBA Feedback for DACA
— 5 FBB Feedback for DACB
— 8 FBC Feedback for DACC
— 9 FBD Feedback for DACD
— 20 FBE Feedback for DACE
— 21 FBF Feedback for DACF
— 24 FBG Feedback for DACG
— 25 FBH Feedback for DACH