Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - DA converter (DAC) TSSOP 20

MAX5580–MAX5585

Buffered, Fast-Settling, Quad,

12-/10-/8-Bit, Voltage-Output DACs

26 ______________________________________________________________________________________

Settling-Time-Mode Write Example:

To configure DACA and DACD into FAST mode and

DACB and DACC into SLOW mode, use the command

in Table 12.

To read back the settling-time-mode bits, use the com-

mand in Table 13.

CPOL and CPHA Control Bits

The CPOL and CPHA control bits of the

MAX5580–MAX5585 are defined the same as the CPOL

and CPHA bits in the SPI standard. Set the DAC’s

CPOL and CPHA bits to CPOL = 0 and CPHA = 0 or

CPOL = 1 and CPHA = 1 for MICROWIRE and SPI

applications requiring the clocking of data in on the ris-

ing edge of SCLK. Set the DAC’s CPOL and CPHA bits

to CPOL = 0 and CPHA = 1 or CPOL = 1 and CPHA =

0 for DSP and SPI applications, requiring the clocking

of data in on the falling edge of SCLK (refer to the

Programmer’s Handbook

and see Table 14 for details).

At power-up, if DSP = DV

, the default value of CPHA

is zero and if DSP = DGND, the default value of CPHA

is one. The default value of CPOL is zero at power-up.

To write to the CPOL and CPHA bits, use the command

in Table 15.

To read back the device’s CPOL and CPHA bits, use

the command in Table 16.

Table 12. Settling-Time-Mode Write Example

DATA CONTROL BITS DATA BITS

DIN1110110XXXXX1001

X = Don’t care.

Table 13. Settling-Time-Mode Read Command

DATA CONTROL BITS DATA BITS

DIN11101111XXXXXXXX

D OU TRBXXXXXXXXX X X X S P D D S P D C S P D BS P D A

Table 16. CPOL and CPHA Read Command

DATA CONTROL BITS DATA BITS

DIN 1 1 1 1 0 0 0 1 X X X X X X X X

D OU TRBXXX XXXXXXXXXXXC P O LC P H A

Table 14. CPOL and CPHA Bits

CPOL CPHA DESCRIPTION

Default values at power-up when DSP is connected to DV

. Data is clocked in on the rising edge

of SCLK.

Default values at power-up when DSP is connected to DGND. Data is clocked in on the falling edge

of SCLK.

1 0 Data is clocked in on the falling edge of SCLK.

1 1 Data is clocked in on the rising edge of SCLK.

Table 15. CPOL and CPHA Write Command

DATA CONTROL BITS DATA BITS

DIN11110000XXXXXXC P O LC P H A

X = Don’t care.