Datasheet

MAX5580–MAX5585
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
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CONTROL BITS DATA BITS
DATA
C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
FUNCTION
INPUT REGISTERS (A–D)
DIN 1 0 1 1 D11 D10 D9 D8 D7 D6 D5 D4 D3/0 D2/0 D1/0 D0/0
Load DACD input register and output register from shift register; DACD output is updated.*
DIN 1 1 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3/0 D2/0 D1/0 D0/0
Load all DAC input registers from the shift register; all DAC output registers are unchanged; all DAC outputs are unchanged.*
DIN 1 1 0 1 D11 D10 D9 D8 D7 D6 D5 D4 D3/0 D2/0 D1/0 D0/0
Load all DAC input and output registers from shift register; DAC outputs are updated.*
CONTROL BITS DATA BITS
DATA
C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Function
SELECT BITS
DIN 111000XXXXXXMDMCMBMA
Load DAC_ output register from input register when M_ is one; DAC_ output register is unchanged if M_ is zero.
SHUTDOWN-MODE BITS
DIN 1 1 1 0 0 1 0 X PDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0
Write DAC_ shutdown- mode bits; see Table 8.
DIN 1110011XXXXXXXXX
DOUTR
X X X X X X X X PDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0
Read DAC_ shutdown- mode bits.
UPIO CONFIGURATION BITS
DIN 1 1 1 0 1 0 0 X UPSL2 UPSL1 UP3 UP2 UP1 UP0 X X
Write UPIO configuration bits; see Table 18.
DIN 1110101XXXXXXXXX
DOUTR
X X X X X X X X UP3-2 UP2-2 UP1-2 UP0-2 UP3-1 UP2-1 UP1-1 UP0-1
Read UPIO configuration bits.
SETTLING-TIME-MODE BITS
DIN 1110110XXXXXSPDD SPDC SPDB SPDA
Write DAC_ settling-time- mode bits; see Table 11.
Table 2b. Advanced-Feature Programming Commands
*
For the MAX5582/MAX5583 (10-bit version), D11–D2 are the significant bits and D1 and D0 are sub-bits. For the MAX5584/MAX5585 (8-bit version),
D11–D4 are the significant bits and D3–D0 are sub-bits. Set all sub-bits to zero during the write commands.
Table 2a. DAC Programming Commands (continued)