Datasheet

MAX5522–MAX5525
Voltage Biasing a
Current-Output Transducer
See the circuit in Figure 5 for an illustration of how to
configure the MAX5524/MAX5525 to bias a current-out-
put transducer. In Figure 5, the output voltage of the
MAX5524/MAX5525 is a function of the voltage drop
across the transducer added to the voltage drop
across the feedback resistor R.
Unipolar Output
Figure 6 shows the MAX5524 in a unipolar output con-
figuration with unity gain. Table 4 lists the unipolar out-
put codes.
Bipolar Output
The MAX5524 output can be configured for bipolar
operation as shown in Figure 7. The output voltage is
given by the following equation:
V
OUT_
= V
REFIN
x [(N
A
- 512) / 512]
where N
A
represents the decimal value of the DAC’s
binary input code. Table 5 shows the digital codes (off-
set binary) and the corresponding output voltage for
the circuit in Figure 7.
Configurable Output Gain
The MAX5524/MAX5525 have force-sense outputs,
which provide a connection directly to the inverting ter-
minal of the output op amp, yielding the most flexibility.
The advantage of the force-sense output is that specific
gains can be set externally for a given application. The
gain error for the MAX5524/MAX5525 is specified in a
unity-gain configuration (op-amp output and inverting ter-
minals connected), and additional gain error results from
external resistor tolerances. Another advantage of the
force-sense DAC is that it allows many useful circuits to
be created with only a few simple external components.
An example of a custom fixed gain using the MAX5524/
MAX5525 force-sense output is shown in Figure 8. In
this example, R1 and R2 set the gain for V
OUTA
.
V
OUTA
= [(V
REFIN
x N
A
) / 1024] x [1 + (R2 / R1)]
where N
A
represents the numeric value of the DAC
input code.
Self-Biased Two-Electrode
Potentiostat Application
See the circuit in Figure 10 for an illustration of how to
use the MAX5525 to bias a two-electrode potentiostat
on the input of an ADC.
Power Supply and
Bypassing Considerations
Bypass the power supply with a 4.7µF capacitor in parallel
with a 0.1µF capacitor to GND. Minimize lengths to reduce
lead inductance. If noise becomes an issue, use shielding
and/or ferrite beads to increase isolation. For the thin QFN
package, connect the exposed pad to ground.
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
18 ______________________________________________________________________________________
Table 4. Unipolar Code Table (Gain = +1)
DAC CONTENTS
MSB LSB
ANALOG OUTPUT
1111 1111 1100 +V
REF
(1023/1024)
1000 0000 0100 +V
REF
(513/1024)
1000 0000 0000 +V
REF
(512/1024) = +V
REF
/2
0111 1111 1100 +V
REF
(511/1024)
0000 0000 0100 +V
REF
(1/1024)
0000 0000 0000 0V
Table 5. Bipolar Code Table (Gain = +1)
DAC CONTENTS
MSB LSB
ANALOG OUTPUT
1111 1111 1100 +V
REF
(511/512)
1000 0000 0100 +V
REF
(1/512)
1000 0000 0000 0V
0111 1111 1100 -V
REF
(1/512)
0000 0000 0100 -V
REF
(511/512)
0000 0000 0000 -V
REF
(512/512) = -V
REF
N
A
IS THE DAC INPUT CODE
(0 TO 1023 DECIMAL).
REFIN
MAX5524
OUT_
FB_
V
OUT
=
V
REFIN
× N
A
1024
DAC
Figure 6. Unipolar Output Circuit