Datasheet

MAX5500/MAX5501
Low-Power, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(MAX5500 (V
DD
= +5V ±10%, V
REFAB
= V
REFCD
= 2.5V), MAX5501 (V
DD
= +3V to +3.6V, V
REFAB
= V
REFCD
= 1.25V), V
AGND
= V
DGND
= 0, R
L
= 5kΩ, C
L
= 100pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values at T
A
= +25°C. Output buffer connected in
unity-gain configuration (Figure 9).)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL OUTPUTS
Output High Voltage V
OH
I
SOURCE
= 2mA V
DD
- 0.5 V
Output Low Voltage V
OL
I
SINK
= 2mA 0.13 0.4 V
DYNAMIC PERFORMANCE
Voltage Output Slew Rate SR 0.6 V/µs
To ±0.5 LSB, V
STEP
= 2.5V
MAX5500A/MAX5500B
12
Output Settling Time
To ±0.5 LSB, V
STEP
= 1.25V
MAX5501A/MAX5501B
16
µs
Output Voltage Swing Rail-to-rail (Note 2) 0 to V
DD
V
Current into FB_ 0 0.1 µA
OUT_ Leakage Current in
Shutdown
R
L
= ∞ ±0.01 ±1.0 µA
MAX5500A/MAX5500B 15
Startup Time Exiting
Shutdown Mode
MAX5501A/MAX5501B 20
µs
Digital Feedthrough CS =V
DD
, f
IN
= 100kHz 5 nV•s
Digital Crosstalk 5nV•s
POWER SUPPLIES
MAX5500A/MAX5500B 4.5 5.5
Supply Voltage V
DD
MAX5501A/MAX5501B 3.0 3.6
V
Supply Current I
DD
(Note 3) 0.85 1.1 mA
Supply Current in Shutdown (Note 3) 10 20 µA
TIMING CHARACTERISTICS (Figure 6)
SCLK Clock Period t
CP
100 ns
SCLK Pulse-Width High t
CH
40 ns
SCLK Pulse-Width Low t
CL
40 ns
CS Fall to SCLK Rise Setup
Time
t
CSS
40 ns
SCLK Rise to CS Rise Hold
Time
t
CSH
0ns
DIN Setup Time t
DS
40 ns
DIN Hold Time t
DH
0ns