Datasheet

MAX5436–MAX5439
±15V, 128-Tap, Low-Drift Digital Potentiometers
_______________________________________________________________________________________ 3
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltage V
CC
= 2.7V to 3.6V 2.0 V
Input Low Voltage V
CC
= 2.7V to 3.6V 0.6 V
Input Leakage Current ±1.0 µA
Input Capacitance 5.0 pF
DYNAMIC CHARACTERISTICS (analog)
R
HL
= 50kΩ, midscale, V
H
= 1.5V
P-P
,
C
WIPER
= 20pF, voltage-divider mode
400
Wiper -3dB Bandwidth BW
W
R
HL
= 100kΩ, midscale, V
H
= 1.5V
P-P
,
C
WIPER
= 20pF, voltage-divider mode
200
kHz
Wiper Settling Time t
IL
C
WIPER
= 20pF, code 1 to code 127, settle
to 0.5LSB
5µs
AMPLIFIER CHARACTERISTICS (analog)
Input Bias Current I
B
15 nA
Input Offset Voltage V
OS
±6mV
Offset-Voltage Temperature Drift V
OSD
10 µV/°C
Input Offset Current I
OS
2nA
Unity-Gain Bandwidth UBW
A
C
LOAD
= 250pF 100 kHz
Slew Rate SR 0.25 V/µs
Large-Signal Voltage Gain A
VO
R
LOAD
= 100kΩ, V
OUT
= ±14V 100 V/mV
Input Noise V
N
f = 1kHz 110 nV/√Hz
Input Compliance CMR
I
V
SS
+ 1 V
DD
- 2 V
Output Compliance CMR
O
I
LOAD
= ±5mA V
SS
+ 1 V
DD
- 1 V
DC CMRR CMRR 68 dB
DC PSRR PSRR 70 dB
TIMING CHARACTERISTICS (digital) (Note 5, Figure 3)
SCLK Clock Frequency f
CLK
0 10 MHz
SCLK Clock Period t
CP
100 ns
SCLK Pulse Width High t
CH
40 ns
SCLK Pulse Width Low t
CL
40 ns
CS Fall to SCLK Rise Setup Time t
CSS
40 ns
SCLK Rise to CS Rise Hold Time t
CSH
10 ns
DIN Setup Time t
DS
40 ns
DIN Hold Time t
DH
0ns
SCLK Rise to CS Fall Delay t
CSO
10 ns
CS Rise to SCLK Rise Hold t
CS1
40 ns
CS Pulse Width High t
CSW
100 ns
POWER SUPPLIES
Positive Analog Supply Voltage V
DD
0 31.5 V
Negative Analog Supply Voltage V
SS
-28.8 0 V
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +15V, V
SS
= -15V, V
CC
= +5V, V
H
= V
DD
, V
L
= V
SS
, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at
T
A
= +25°C, unless otherwise noted.)