Datasheet

Digital Interface Operation
The MAX5430/MAX5431 feature a simple two-bit paral-
lel programming interface. D1 and D0 program the gain
setting according to the Logic-Control Truth Table (see
Table 1). The digital interface is CMOS/TTL logic com-
patible.
Applications Information
Programmable-Gain Amplifier
The MAX5430/MAX5431 are ideally suited for high-pre-
cision PGA applications. The typical application circuit
of Figure 2 uses the MAX5431 with matching resistor to
compensate for voltage offset due to op amp input bias
currents. Use the MAX5430 with an ultra-low input bias
current op amp (see Figure 3).
Power Supplies and Bypassing
The MAX5430/MAX5431 operate from dual ±15V sup-
plies or a single 15V supply. For dual supplies, bypass
V
DD
and V
SS
with 0.1µF ceramic capacitors to GND.
For single supply, connect V
SS
to GND and bypass
V
DD
with a 0.1µF ceramic capacitor to GND.
Switching Time and Layout Concerns
The switching time of the MAX5430/MAX5431 depends
on the capacitive loading at W. For best performance,
reduce parasitic board capacitance by minimizing the
circuit board trace from W to the op amp inverting input,
and choose an op amp with low input capacitance.
MAX5430/MAX5431
±15V Digitally Programmable
Precision Voltage-Dividers for PGAs
6 _______________________________________________________________________________________
15V
MATCH_L
W
H
15V
MATCH_H
V
SS
V
DD
GNDL
MAX5431
V
IN
V
OUT
15V
W
H
15V
V
SS
V
DD
GNDL
MAX5430
V
IN
V
OUT
Figure 2. MAX5431 Typical Application Circuit PGA with Input
I
BIAS
Matching
Figure 3. Programmable-Gain Amplifier Using the MAX5430
1
2
8
7
SOT23
TOP VIEW
3
4
6
5
MAX5430
V
DD
D0
V
SS
L
H
W
D1 GND
Pin Configurations (continued)
Chip Information
TRANSISTOR COUNT: 121
PROCESS: CMOS