Datasheet

MAX5422/MAX5423/MAX5424
(CS), data clock (SCLK), and data in (DIN). Drive CS
low to enable the serial interface and clock data syn-
chronously into the shift register on each SCLK rising
edge.
The WRITE commands (C1, C0 = 00 or 01) require 16
clock cycles to clock in the command and data (Figure
2a). The COPY commands (C1, C0 = 10, 11) can use
either eight clock cycles to transfer the command bits
(Figure 2b) or 16 clock cycles with 8 data bits that are
disregarded by the device (Figure 2a).
After loading data into the shift register, drive CS high
to latch the data into the appropriate potentiometer
control register and disable the serial interface. Keep
CS low during the entire serial-data stream to avoid
corruption of the data.
The serial-data timing for the potentiometer is shown in
Figures 1 and 2.
256-Tap, Nonvolatile, SPI-Interface,
Digital Potentiometers
8 _______________________________________________________________________________________
CLOCK EDGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Bit name — — C1 C0 — — — — D7 D6 D5 D4 D3 D2 D1 D0
Write wiper register 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0
Write NV register 0 0 0 1 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0
Copy wiper register to NV
register
00100000————————
Copy NV register to wiper
register
00110000————————
Table 1. Register Map
1 2 3 4 5 6 7 8 9 10111213141516
D7 D6 D5 D4 D3 D2 D1 D0C1 C0
SCLK
DIN
A) 16-BIT COMMAND/DATA WORD
12345678
C1 C0
SCLK
DIN
B) 8-BIT COMMAND WORD
CS
CS
Figure 2. Digital-Interface Format