Datasheet

Switching Time and Layout Concerns
The switching time of the MAX5420/MAX5421 depends
on the capacitive loading at W. For best performance,
reduce parasitic board capacitance by minimizing the
circuit board trace from W to the op amp inverting input,
and choose an op amp with low input capacitance.
Chip Information
TRANSISTOR COUNT: 118
PROCESS: CMOS
MAX5420/MAX5421
Digitally Programmable Precision
Voltage Divider for PGAs
V
OUT
+5V
MATCH_L
H
V
DD
+5V
MATCH_H
L
V
SS
W
GND
MAX5421
V
IN
MAX4493
H
W
L
GND
+5V
+5V
MAX5420
V
DD
V
SS
V
IN
MAX4237
V
OUT
Figure 3. Programmable-Gain Amplifier with Op Amp Bias-
Current Matching
Figure 4. Programmable-Gain Amplifier
R1AR2AR3A
L
H
R3B
R2B R1B
RATIO = 1
RATIO = 2
RATIO = 4
RATIO = 8
W
RATIO =
R_B
R_A
1+
( )
Figure 1. Simplified Functional Diagram
R1AR2AR3A
L
H
R3B
R2B R1B
RATIO = 1
RATIO = 2
RATIO = 4
RATIO = 8
W
RATIO =
R_B
R_A
1+
( )
0.1µF
+5V
V
DD
0.1µF
-5V
V
SS
GND
PULSE
GENERATOR
D1 D0
MAX5421
TEKTRONIX P6245
OSCILLOSCOPE FET
PROBE
C
L
< 1pF
1MΩ
Figure 2. Switching Time Test Circuit
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