Datasheet

MAX5403/MAX5404/MAX5405
of each SCLK pulse (Figure 2). After all the data bits
have been shifted in, they are latched into the appropri-
ate potentiometer control register when CS transitions
from low to high. Note that if CS is not kept low during
the entire data stream, the data will be corrupted and
the device will need to be reloaded.
The first bit A0 (address bit) is used to address one or
the other of the potentiometers for programming.
Potentiometer control register A is selected for writing
when A0 is ‘zero’, and potentiometer control register B
is selected when A0 is one.
The MAX5403/MAX5404/MAX5405 feature POR circuitry
that sets the wiper to the midscale position at power-up.
Applications Information
The MAX5403/MAX5404/MAX5405 are intended for a
variety of circuits where accurate, fine-tuning adjustable
resistance is required, such as in adjustable voltage or
adjustable gain circuit configurations. It is primarily used
in either a potentiometer divider or a variable resistor
configuration.
Adjustable Current to Voltage Converter
Figure 5 shows the MAX5403/MAX5404/MAX5405 being
used with a MAX4250 low-noise op amp to fine tune a
current to voltage converter. Pins H
B
and W
B
of the
MAX5403/MAX5404/MAX5405 3-terminal potentiometer
(only pin W
A
of the 2-terminal variable resistor) are con-
nected to the node between R3 and R2 (pin L
X
is con-
nected to ground). Circuit space is minimized due to
both devices’ packaging.
Adjustable Gain Amplifier
Figure 6 shows how to use the MAX5403/MAX5404/
MAX5405 to digitally adjust the gain of a noninverting op
amp configuration. In Figure 6a, connect the MAX5403/
MAX5404/MAX5405 as a 2-terminal variable resistor in
series with a resistor to ground to form the adjustable
gain control of a noninverting amplifier.
Similarly, Figure 6b shows how to use the MAX5403/
MAX5404/MAX5405 as a 3-terminal potentiometer. In
this application the MAX5403/MAX5404/MAX5405 low
5ppm/°C ratiometric tempco allows for a very stable
adjustable gain-configuration overtemperature.
Dual 256-Tap, Low-Drift,
Digital Potentiometers in 10-µMAX
8 _______________________________________________________________________________________
SCLK
POT REGISTER LOADED
9TH CLOCK PULSE1ST CLOCK PULSE
DIN
TIME
A0 D7 D6 D5 D4 D3 D2 D1 D0
CS
MSB LSB
Figure 2. Potentiometer Serial Data Timing Circuit
• • •
• • •
• • •
CS
SCLK
DIN
t
CSO
t
CSS
t
CL
t
DS
t
DH
t
CH
t
CSH
t
CSW
t
CP
t
CS1
Figure 3. Detailed Serial Interface Timing Diagram