Datasheet

Functional Diagram
Detailed Description
The MAX5395 single, 256-tap volatile, low-voltage
linear taper digital potentiometer offers three end-to-
end resistance values of 10kΩ, 50kΩ, and 100kΩ.
Potentiometer terminals are independent of supply for
voltages up to +5.25V with single-supply operation from
1.7V to 5.5V (charge pump enabled). User-controlled
shutdown modes allow the H, W, or L terminals to be
opened with the wiper position set to zero-code, midcode,
full-code, or the value contained in the wiper register. Ultra-
low-quiescent supply current (< 1µA) can be achieved for
supply voltages between 2.6V and 5.5V by disabling the
internal charge pump and not allowing potentiometer
terminals to exceed the supply voltage by more than
0.3V. The MAX5395 provides a low 50ppm/°C end-to-end
temperature coefficient and features a I
2
C serial interface.
The small package size, low supply operating voltage,
low supply current, and automotive temperature range
of the MAX5395 make the device uniquely suited for the
portable consumer market and battery-backup industrial
applications.
Charge Pump
The MAX5395 contains an internal charge pump that
guarantees the maximum wiper resistance, R
WL
, to be
less than 50Ω (25Ω typ) for supply voltages down to
1.7V and allows pins H, W, and L to be driven between
GND and 5.25V independent of V
DD
. Minimal charge-
pump feedthrough is present at the terminal outputs
and is illustrated by the Charge-Pump Feedthrough
at W vs. Frequency graph in the Typical Operating
Characteristics. The charge pump is on by default but
can be disabled with QP_OFF and enabled with the
QP_ON commands (Table 1). The MAX5395 minimum
supply voltage with charge pump disabled is limited
to 2.6V and terminal voltage cannot exceed -0.3V to
(V
DD
+ 0.3V).
I
2
C Interface
The MAX5395 feature an I
2
C/SMBus-compatible, 2-wire
serial interface consisting of a serial data line (SDA) and
a serial clock line (SCL). SDA and SCL enable commu-
nication between the MAX5395 and the master at clock
rates up to 400kHz. Figure 1 shows the 2-wire interface
timing diagram. The master generates SCL and initiates
data transfer on the bus. The master device writes data
to the MAX5395 by transmitting the proper slave address
followed by the command byte and then the data word.
Each transmit sequence is framed by a START (S) or
Repeated START (Sr) condition and a STOP (P) condi-
tion. Each word transmitted to the MAX5395 is 8 bits long
and is followed by an acknowledge clock pulse. A master
reading data from the MAX5395 must transmit the proper
slave address followed by a series of nine SCL pulses for
each byte of data requested. The MAX5395 transmit data
on SDA in sync with the master-generated SCL pulses.
The master acknowledges receipt of each byte of data.
Each read sequence is framed by a START or Repeated
START condition, a not acknowledge, and a STOP condi-
tion. SDA operates as both an input and an open-drain
output. A pullup resistor, typically 4.7kΩ, is required on
SDA. SCL operates only as an input. A pullup resistor,
typically 4.7kΩ, is required on SCL if there are multiple
masters on the bus, or if the single master has an open-
drain SCL output.
Series resistors in line with SDA and SCL are optional.
Series resistors protect the digital inputs of the MAX5395
from high voltage spikes on the bus lines and mini-
mize crosstalk and undershoot of the bus signals. The
MAX5395 can accommodate bus voltages higher than
V
DD
up to a limit of +5.5V. Bus voltages lower than V
DD
are not recommended and may result in significantly
increased interface currents and data corruption.
The MAX5395 with I
2
C interface contains a shift register
that decodes the command and address bytes, routing
the data to the register. Data written to a memory register
immediately updates the wiper position. The wiper powers
up in mid position, D[7:0] = 0x80 with charge pump enabled.
H
L
ADDRO
GND
SDA
W
V
DD
SCL
MAX5395
I
2
C
INTERFACE
MAX5395 Single, 256-Tap Volatile, I
2
C, Low-Voltage Linear
Taper Digital Potentiometer
www.maximintegrated.com
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