Datasheet

(V
DD
= 1.7V to 5.5V, V
H
= V
DD
, V
L
= GND, T
A
= -40°C to +125°C, unless otherwise noted. Typical values are at V
DD
= 1.8V,
T
A
= +25°C.) (Note 2)
Note 2: All devices are production tested at T
A
= +25°C and are guaranteed by design and characterization for T
A
= -40°C to
+125°C.
Note 3: DNL and INL are measured with the potentiometer configured as a voltage-divider with V
H
= 5.25 (QP enabled) or V
DD
(QP disabled) and V
L
= GND. The wiper terminal is unloaded and measured with an ideal voltmeter.
Note 4: R-DNL and R-INL are measured with the potentiometer configured as a variable resistor (Figure 1). H is unconnected and
L = GND.
For charge pump enabled, V
DD
= 1.7V to 5.5V, the wiper terminal is driven with a source current of 400μA for the 10kΩ
configuration, 80μA for the 50kΩ configuration, and 40μA for the 100kΩ configuration.
For charge pump disabled and V
DD
= 5.5V, the wiper terminal is driven with a source current of 400μA for the 10kΩ
configuration, 80μA for the 50kΩ configuration, and 40μA for the 100kΩ configuration.
For charge pump disabled and V
DD
= +2.6V, the wiper terminal is driven with a source current of 200μA for the 10kΩ
configuration, 40μA for the 50kΩ configuration, and 20μA for the 100kΩ configuration.
Note 5: The wiper resistance is the maximum value measured by injecting the currents given in Note 4 into W with L = GND.
R
W
= (V
W
- V
H
)/I
W
.
Note 6: Measured at W with H driven with a 1kHz, 0V to V
DD
amplitude tone and V
L
= GND. Wiper at midscale with a 10pF load.
Note 7: Wiper-settling time is the worst-case 0-to-50% rise time, measured between tap 0 and tap 127. H = V
DD
, L = GND, and the
wiper terminal is loaded with 10pF capacitance to ground.
Note 8: Digital inputs at V
DD
or GND.
Note 9: Digital timing is guaranteed by design and characterization, and is not production tested.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS (Note 9)
SCLK Frequency f
SCLK
2.6V < V
DD
< 5.5V 50
MHz
1.7V < V
DD
< 2.6V 25
SCLK Period t
SCLK
2.6V < V
DD
< 5.5V 20
ns
1.7V < V
DD
< 2.6V 40
SCLK Pulse-Width High t
CH
8 ns
SCLK Pulse-Width Low t
CL
8 ns
CS Fall to SCLK Fall Setup
Time
t
CSS0
To 1st SCLK falling
edge (FE)
2.6V < V
DD
< 5.5V 8
ns
1.7V < V
DD
< 2.6V 16
CS Fall to SCLK Fall Hold
Time
t
CSH0
Applies to inactive FE preceding 1st FE 0 ns
CS Rise to SCLK Fall Hold
Time
t
CSH1
Applies to 16th FE 0 ns
CS Rise to SCLK Fall
t
CSA
Applies to 16th FE,
aborted sequence
2.6V < V
DD
< 5.5V 12
ns
1.7V < V
DD
< 2.6V 16
SCLK Fall to CS Fall
t
CSF
Applies to 16th FE 100 ns
CS Pulse-Width High
t
CSPW
20 ns
DIN to SCLK Fall Setup Time t
DS
5 ns
DIN to SCLK Fall Hold Time t
DH
4.5 ns
CS Pulse-Width High
t
CSPW
20 ns
MAX5394 Single, 256-Tap Volatile, SPI, Low-Voltage Linear
Taper Digital Potentiometer
www.maximintegrated.com
Maxim Integrated │ 4
Electrical Characteristics (continued)