Datasheet

Detailed Description
The MAX5387 dual, 256-tap, volatile, low-voltage linear
taper digital potentiometer offers three end-to-end resis-
tance values of 10kΩ, 50kΩ, and 100kΩ. The potenti-
ometer consists of 255 fixed resistors in series between
terminals H_ and L_. The potentiometer wiper, W_, is
programmable to access any one of the 256 tap points on
the resistor string.
The potentiometers are programmable independently of
each other. The MAX5387 features an I
2
C interface.
I
2
C Digital Interface
The I
2
C interface contains a shift register that decodes
the command and address bytes, routing the data to the
appropriate control registers. Data written to a control
register immediately updates the wiper position. Wipers A
and B power up in midposition, D[7:0] = 80H.
Serial Addressing
The MAX5387 operates as a slave device that receives
data through an I
2
C-/SMBus™-compatible 2-wire serial
interface. The interface uses a serial-data access (SDA)
line and a serial-clock line (SCL) to achieve bidirectional
communication between master(s) and slave(s). A mas-
ter, typically a microcontroller, initiates all data transfers
to the MAX5387, and generates the SCL clock that syn-
chronizes the data transfer (Figure 2).
The MAX5387 SDA line operates as both an input and an
open-drain output. The SDA line requires a pullup resistor,
typically 4.7kΩ. The MAX5387 SCL line operates only as
an input. The SCL line requires a pullup resistor (typically
4.7kΩ) if there are multiple masters on the 2-wire inter-
face, or if the master in a single-master system provides
an open-drain SCL output.
Each transmission consists of a START (S) condition
(Figure 3) sent by a master, followed by the MAX5387
7-bit slave address plus the NOP/W bit (Figure 6), 1
command byte and 1 data byte, and finally a STOP (P)
condition (Figure 3).
START and STOP Conditions
SCL and SDA remain high when the interface is inactive.
A master controller signals the beginning of a transmis-
sion with a START condition by transitioning SDA from
high to low while SCL is high. The master controller issues
a STOP condition by transitioning the SDA from low to
high while SCL is high, after finishing communicating with
the slave. The bus is then free for another transmission.
SMBus is a trademark of Intel Corp.
Figure 2. I
2
C Serial Interface Timing Diagram
SDA
SCL
START
CONDITION
(S)
t
LOW
t
BUF
t
HIGH
t
HD:STA
t
HD:STA
t
SU:DAT
t
R
t
F
t
SU:STD
REPEATED
START CONDITION
(Sr)
ACKNOWLEDGE (A) STOP CONDITION
(P)
START CONDITION
(S)
t
HD-DAT
t
SU:DTA
MAX5387 Dual, 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometer
www.maximintegrated.com
Maxim Integrated │ 9